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Research Papers

The Effects of Temperature Cyclic Loading on Lead-Free Solder Joints of Wafer Level Chip Scale Package by Taguchi Method

[+] Author and Article Information
Wen-Ren Jong

Department of Mechanical Engineering, Chung Yuan Christian University, Chung-Li, Taiwan; R&D Center for Mold and Molding Technology, Chung-Yuan Christian University, Chung-Li, Taiwanwenren@cycu.edu.tw

Hsin-Chun Tsai

Department of Mechanical Engineering, Minghsin University of Science and Technology, Hsin-Chu, Taiwan

Hsiu-Tao Chang, Shu-Hui Peng

Department of Mechanical Engineering, Chung Yuan Christian University, Chung-Li, Taiwan

J. Electron. Packag 130(1), 011001 (Jan 31, 2008) (10 pages) doi:10.1115/1.2837508 History: Received December 13, 2005; Revised August 21, 2007; Published January 31, 2008

In this study, the effects of the temperature cyclic loading on three lead-free solder joints of 96.5Sn–3.5Ag, 95.5Sn–3.8Ag-0.7Cu, and 95.5Sn–3.9Ag-0.6Cu bumped wafer level chip scale package (WLCSP) on printed circuit board assemblies are investigated by Taguchi method. The orthogonal arrays of L16 is applied to examine the shear strain effects of solder joints under five temperature loading parameters of the temperature ramp rate, the high and low temperature dwells, and the dwell time of both high and low temperatures by means of three simulated analyses of creep, plastic, and plastic-creep behavior on the WLCSP assemblies. It is found that the temperature dwell is the most significant factor on the effects of shear strain range from these analyses. The effect of high temperature dwell on the shear strain range is larger than that of low temperature dwell in creep analysis, while the effect of high temperature dwell on the shear strain range is smaller than that of low temperature dwell in both plastic and plastic-creep analyses.

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Copyright © 2008 by American Society of Mechanical Engineers
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Figures

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Figure 10

S∕N response chart for five factors in the creep, plastic, and plastic-creep analyses, respectively

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Figure 9

Elapsed CPU time and shear creep strain range of various simplified models

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Figure 8

Shear stress and shear creep strain hysteresis loops on WLCSP with 96.5Sn–3.5Ag solder in 3D model: (a) one-eighth model (Type 1), (b) one-eighth model (Type 2), (c) one-eighth model (Type 3), (d) one-eighth model (Type 4), (e) one-quarter model, and (f) full model

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Figure 7

WLCSP in 2D for the verification of models: (a) finite element model of a half of WLCSP and boundary conditions; (b) shear stress and creep shear strain hysteresis loops for 62Sn–36Pb–2Ag, (c) for 96.5Sn–3.5Ag, and (d) for 100In corner solder joints

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Figure 6

Temperature cyclic loading for the verification of models

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Figure 5

Analytic setting of 16 different temperature cyclic loadings for the L16-orthogonal arrays

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Figure 1

The dimension and schematic of a chip model on WLCSP

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Figure 4

Variety of finite element models and boundary conditions: (a) one-eighth model (Type 1), (b) one-eighth model (Type 2), (c) one-eighth model (Type 3), (d) one-eighth model (Type 4 with elements of 7897 and nodes of 10,168), (e) one-quarter model, and (f) full model

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Figure 3

Distribution of solder joint of one-eighth model with four types of a chip on WLCSP assembly: (a) the entire (Type 1), (b) only two rows of the entire (Type 2), (c) simplified three arrays (Type 3), and (d) only two rows with simplified three arrays (Type 4) solder joints

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Figure 2

The cross section of a chip on WLCSP and dimensions of the solder joint: (a) cross section and (b) sizes of pad and solder joint

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