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RESEARCH PAPERS

A Theoretical Analysis of the Concept of Critical Clearance Toward a Design Methodology for the Flip-Chip Package

[+] Author and Article Information
J. W. Wan

College of Civil Engineering,  Guangzhou University, Guangzhou, Guangdong, China

W. J. Zhang

Department of Mechanical Engineering,  University of Saskatchewan, Saskatoon, Saskatchewan, Canada; College of Mechanical and Power Engineering,  East China University of Science and Technology, Shanghai, China

D. J. Bergstrom

Department of Mechanical Engineering,  University of Saskatchewan, Saskatoon, Saskatchewan, Canada

J. Electron. Packag 129(4), 473-478 (Mar 13, 2007) (6 pages) doi:10.1115/1.2804098 History: Received December 12, 2006; Revised March 13, 2007

In this article, we present a theoretical study on the concept known as critical clearance for flip-chip packages. The critical clearance phenomenon was first observed in an experiment reported by Gordon (1999, “A Capillary-Driven Underfill Encapsulation Process  ,” Advanced Packaging, 8(4), pp. 34–37). When the clearance is below a critical value, filling time begins to increase dramatically, and when the clearance is above this value, the influence of clearance on filling time is insignificant. Therefore, the optimal solder bump density in a flip-chip package should be one with a clearance larger than the critical clearance. The contribution of our study is the development of a quantitative relation among package design features, flow characteristics, and critical clearance based on an analytical model we developed and reported elsewhere. This relation is further used to determine critical clearance given a type of underfill material (specifically the index n of the power-law constitutive equation), the solder bump pitch, and the gap height; further the flip-chip package design can be optimized to make the actual clearance between solder bumps greater than its corresponding critical clearance.

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Copyright © 2007 by American Society of Mechanical Engineers
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Figures

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Figure 1

Full array flip-chip package

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Figure 2

Effect of the solder bump pitch on the filling time

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Figure 3

Effect of the solder bump pitch on the filling time

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Figure 4

Effect of the solder bump diameter on the filling time

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Figure 5

Effect of the solder bump diameter on the filling time

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Figure 6

Effect of the clearance on the filling time

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Figure 7

Simulated flow front at 30s elapsed flow time with respect to several cases of clearances ((a) clearance, 50μm; (b) clearance, 60μm; (c) clearance, 70μm)

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Figure 8

Filling time versus clearance of flip-chip package (gap height, 75μm; bump diameter, 125μm)

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Figure 9

Effect of the dimensionless clearance on the dimensionless filling time for different dimensionless gap heights

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Figure 10

Dimensionless critical clearance versus dimensionless gap height

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Figure 11

Dimensionless critical clearance versus dimensionless gap height

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Figure 12

Wcritical∗∕[(n+1)∕n] versus dimensionless gap height

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Figure 13

The flowchart for flip-chip package design

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