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RESEARCH PAPERS

A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance

[+] Author and Article Information
Karan Kacker, Thomas Sokol

Computer Aided Simulation of Packaging Reliability (CASPaR) Laboratory, The George W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0405

Wansuk Yun, Madhavan Swaminathan

School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332

Suresh K. Sitaraman

Computer Aided Simulation of Packaging Reliability (CASPaR) Laboratory, The George W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0405suresh.sitaraman@me.gatech.edu

J. Electron. Packag 129(4), 460-468 (Apr 09, 2007) (9 pages) doi:10.1115/1.2804096 History: Received October 28, 2006; Revised April 09, 2007

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

Copyright © 2007 by American Society of Mechanical Engineers
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References

Figures

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Figure 1

Schematic of a G-Helix interconnect

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Figure 2

Fabrication process for variable interconnect design

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Figure 3

Mechanical test vehicle design for heterogeneous Interconnects

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Figure 4

Electrical test vehicle design for heterogeneous interconnects

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Figure 5

Preliminary fabrication results for mechanical test vehicle die

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Figure 6

Meshed GPD model of heterogenous interconnect package

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Figure 7

Boundary conditions on GPD models

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Figure 8

Equivalent plastic strain distribution at the end of third thermal cycle

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Figure 9

Sxx stress in the die

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Figure 10

Fabricated helix interconnect for compliance measurement

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Figure 11

Force versus displacement in the out-of-plane direction

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Figure 12

Fabricated 100μm pitch G-Helix interconnects

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Figure 13

Substrate layout

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Figure 14

Substrate cross section with surface finish

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Figure 15

Approximate assembly force and temperature profile

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Figure 16

Cross section of assembled G-Helix interconnects

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Figure 17

% working versus number of cycles

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