Placing active circuitry directly underneath the bond pads is an effective way to reduce the die size, and hence to achieve lower cost per chip. The main concern with such design is the possible mechanical damage to the underlying circuitry during the wire bonding process. For example, the initial bond force and subsequent ultrasonic vibration may cause cracks within the dielectric layer. The cracks can penetrate through the active circuitry underneath, resulting in electrical failures to the silicon device. In this paper, a finite element based methodology was developed to study the stress behavior of bond pad structures during thermosonic wire bonding. The focus of our analysis is on dielectric layer crack, which was the dominant failure mode observed. The finite element (FE) model is 3-D based and contains the wire ball, the bond pad, and the underpad structure. The model was subjected to various bond force/ultrasound conditions, and the stresses were compared with the percentage of cracked pads in the real life bonding experiments. By using the volume-averaged, incremental first principal stress at the dielectric layer as the stress criterion, we achieved a reasonably good correlation with the experiments. In addition, we found that the dynamic friction at the bond interface is critical in stress distributions at the bond pad. Based on this, we have provided an explanation on how stresses progress during a typical bond force. Furthermore, the stress progression pattern was shown to correlate well with the different crack patterns. The FE model established a baseline upon which more designs with bonding over active circuitry can be analyzed and evaluated for crack resistance to thermosonic wire bonding.
