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RESEARCH PAPERS

Analytical and Experimental Characterization of Bonding Over Active Circuitry

[+] Author and Article Information
Li Zhang, Vijaylaxmi Gumaste, Anindya Poddar, Luu Nguyen

 National Semiconductor Corp., Santa Clara, CA 95052

Gary Schulze

 Kulicke and Soffa Industries, Willow Grove, PA 19090

J. Electron. Packag 129(4), 391-399 (Nov 28, 2006) (9 pages) doi:10.1115/1.2753886 History: Received October 02, 2005; Revised November 28, 2006

Placing active circuitry directly underneath the bond pads is an effective way to reduce the die size, and hence to achieve lower cost per chip. The main concern with such design is the possible mechanical damage to the underlying circuitry during the wire bonding process. For example, the initial bond force and subsequent ultrasonic vibration may cause cracks within the dielectric layer. The cracks can penetrate through the active circuitry underneath, resulting in electrical failures to the silicon device. In this paper, a finite element based methodology was developed to study the stress behavior of bond pad structures during thermosonic wire bonding. The focus of our analysis is on dielectric layer crack, which was the dominant failure mode observed. The finite element (FE) model is 3-D based and contains the wire ball, the bond pad, and the underpad structure. The model was subjected to various bond force/ultrasound conditions, and the stresses were compared with the percentage of cracked pads in the real life bonding experiments. By using the volume-averaged, incremental first principal stress at the dielectric layer as the stress criterion, we achieved a reasonably good correlation with the experiments. In addition, we found that the dynamic friction at the bond interface is critical in stress distributions at the bond pad. Based on this, we have provided an explanation on how stresses progress during a typical bond force. Furthermore, the stress progression pattern was shown to correlate well with the different crack patterns. The FE model established a baseline upon which more designs with bonding over active circuitry can be analyzed and evaluated for crack resistance to thermosonic wire bonding.

Copyright © 2007 by American Society of Mechanical Engineers
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References

Figures

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Figure 1

Schematic view of the bond pad stack for test chip A

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Figure 2

Schematic view of the bond pad stack for test chip B

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Figure 3

Normalized ball shear for test chip A

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Figure 4

Normalized ball shear for test chip B

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Figure 5

Test chip A—percentage dielectric cracks

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Figure 6

Test chip B—percentage dielectric cracks

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Figure 7

Typical dielectric crack pattern for test chip A

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Figure 8

Typical dielectric crack pattern for test chip B

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Figure 9

IMC and normalized ball shear correlation for test chip A

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Figure 10

A 3-D view of the finite element model for test chip A

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Figure 11

Deformed ball and stress contour plots at the end of load step 2 (top) and the end of load step 4 (bottom)

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Figure 12

First principal stress at the bond pad under different friction coefficients, low force/low ultrasound

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Figure 13

First principal stress at the bond pad under different friction coefficients, high force/high ultrasound

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Figure 14

Contact status under low friction coefficient (top), medium friction coefficient (middle), and high friction coefficient (bottom), low force and low ultrasound are assumed

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Figure 15

Stress-crack correlation for test chip A

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