On-Wafer Capacitors Under Mechanical Stress

[+] Author and Article Information
Päivi H. Karjalainen

Institute of Electronics, Tampere University of Technology, P.O. Box 692, FIN-33101 Tampere, Finland

Pekka Heino

Institute of Electronics, Tampere University of Technology, P.O. Box 692, FIN-33101 Tampere, Finlandpaivi.karjalainen@tut.fi

J. Electron. Packag 129(3), 287-290 (Aug 24, 2006) (4 pages) doi:10.1115/1.2753918 History: Received April 24, 2006; Revised August 24, 2006

New packaging materials make it possible to produce flexible system in package (SIP) and system on package (SOP) modules. However, in these the integrated circuits are exposed to increased mechanical stresses. The stresses may become even more severe when thinned chips are used. The effect of mechanical stress on the characteristics of on-wafer capacitors was studied. The mechanical stress increased clearly the resonance frequency of poly-insulator-poly capacitors, but caused only minor impedance changes for metal-insulator-metal capacitors. No fatal stress-induced phenomenon was found and the on-wafer capacitors should also operate correctly in SIP and SOP modules. The test chips were processed with two different complementary metal oxide semiconductor processes and the tested on-wafer capacitors had values of 4.847pF.

Copyright © 2007 by American Society of Mechanical Engineers
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Figure 1

Basic sketch of the 4PB fixture

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Figure 2

Capacitors C1 (47pF) and C2 (10pF) without stress and with loads of 201.1g (stressed) and 301.3g (hard stressed)

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Figure 3

Basic layout of the PIP capacitors with GSG pads

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Figure 4

Capacitors C6 (8pF) and C8 (4.8pF) without stress and with loads of 301.3g (stressed)

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Figure 5

Capacitors C4 (8.5pF) and C5 (8.5pF) without stress and with loads of 301.3g (stressed)



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