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TECHNICAL BRIEF

Investigations of Board-Level Drop Reliability of Wafer-Level Chip-Scale Packages

[+] Author and Article Information
Yi-Shao Lai1

Stress-Reliability Lab, Advanced Semiconductor Engineering, Inc., 26 Chin 3rd Road, Nantze Export Processing Zone, 811 Nantze, Kaohsiung, Taiwanyishao_lai@aseglobal.com

Chang-Lin Yeh, Ching-Chun Wang

Stress-Reliability Lab, Advanced Semiconductor Engineering, Inc., 26 Chin 3rd Road, Nantze Export Processing Zone, 811 Nantze, Kaohsiung, Taiwan

1

Corresponding author.

J. Electron. Packag 129(1), 105-108 (Jun 06, 2006) (4 pages) doi:10.1115/1.2429717 History: Received January 22, 2006; Revised June 06, 2006

We present in this paper parametric studies of board-level reliability of wafer-level chip-scale packages subjected to a specific pulse-controlled drop test condition. Eighteen experiment cells, constructed by varying joint pitch, die thickness, and die size, are proposed and examined numerically. The transient analysis follows the support excitation scheme and incorporates an implicit time integration solver. Numerical results indicate that the drop reliability of the package enhances as the die thickness as well as the die size decreases. Moreover, the package with smaller solder joints and a smaller joint pitch suffers a greater drop reliability concern.

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Copyright © 2007 by American Society of Mechanical Engineers
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Figures

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Figure 2

Finite element model around package

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Figure 3

Schematic of failure modes

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Figure 4

Envelopes of σn (in MPa) on package side (left) and test board side (right) for cell I1

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Figure 5

Envelopes of σs (in MPa) on package side (left) and test board side (right) for cell I1

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Figure 1

Schematic of solder joint

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Figure 6

Envelopes of ϵp (in %) on package side (left) and test board side (right) for cell I1

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Figure 7

Maximum σn for different cells

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Figure 8

Maximum σs for different cells

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Figure 9

Maximum ϵp for different cells

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