0
RESEARCH PAPERS

An Exergy-Based Figure-of-Merit for Electronic Packages

[+] Author and Article Information
Amip J. Shah

Department of Mechanical Engineering, University of California, Berkeley, California 94720-1740amipshah@me.berkeley.edu

Van P. Carey

Department of Mechanical Engineering, University of California, Berkeley, California 94720-1740vcarey@me.berkeley.edu

Cullen E. Bash

 Hewlett Packard Laboratories, 1501 Page Mill Road, M/S 1183, Palo Alto, California 94304-1126cullen.bash@hp.com

Chandrakant D. Patel

 Hewlett Packard Laboratories, 1501 Page Mill Road, M/S 1183, Palo Alto, California 94304-1126chandrakant.patel@hp.com

J. Electron. Packag 128(4), 360-369 (Dec 13, 2005) (10 pages) doi:10.1115/1.2351901 History: Received May 19, 2005; Revised December 13, 2005

Chip power consumption and heat dissipation have become important design issues because of increased energy costs and thermal management limitations. As a global compute utility evolves, seamless connectivity from the chip to the data center will become increasingly important. The optimization of such an infrastructure will require performance metrics that can adequately capture the thermodynamic and compute behavior at multiple physical length scales. In this paper, an exergy-based figure-of-merit (FoM), defined as the ratio of computing performance (in MIPS) to the thermodynamic performance (in exergy loss), is proposed for the evaluation of computational performance. The paper presents the framework to apply this metric at the chip level. Formulations for the exergy loss in simple air-cooled heat sink packages are developed, and application of the proposed approach is illustrated through two examples. The first comparatively assesses the loss in performance resulting from different cooling solutions, while the second examines the impact of non-uniformity in junction power in terms of the FoM. Modeling results on a 16mm×24mm chip indicate that uniform power and temperature profiles lead to minimal package irreversibility (and therefore the best thermodynamic performance). As the nonuniformity of power is increased, the performance rapidly degrades, particularly at higher power levels. Additionally, the competing needs of minimization of junction temperature and minimization of cooling power were highlighted using the exergy-based approach. It was shown that for a given power dissipation and a specific cooling architecture (such as an air-cooled heat sink solution), an optimal thermal resistance value exists beyond which the costs of increased cooling may outweigh any potential benefits in performance. Thus, the proposed FoM provides insight into thermofluidic inefficiencies that would be difficult to gain from a traditional first-law analysis. At a minimum, the framework presented in this paper enables quantitative evaluation of package performance for different nonuniform power inputs and different choices of cooling parameters. At best, since the FoM is scalable, the proposed metric has the potential to enable a chip-to-data-center strategy for optimal resource allocation.

FIGURES IN THIS ARTICLE
<>
Copyright © 2006 by American Society of Mechanical Engineers
Your Session has timed out. Please sign back in to continue.

References

Figures

Grahic Jump Location
Figure 1

Cross-sectional view of chip package and a simplified thermal resistance network

Grahic Jump Location
Figure 2

Junction-to-ambient energy and exergy flow. Temperature gradients across the different components lead to irreversibilities that destroy exergy. In addition, the friction encountered in the airflow also destroys exergy.

Grahic Jump Location
Figure 3

Exergetic resistance network corresponding to the cooling architecture shown in Fig. 1. Any source of thermofluidic resistance—whether thermal resistance or flow resistance—is also a source of exergy loss, and can therefore conceptually be modeled as an exergetic resistance.

Grahic Jump Location
Figure 4

Nonuniform power dissipation in a typical 100-W dual-core processor

Grahic Jump Location
Figure 5

Thermal and exergetic resistance distribution in the dual-core chip

Grahic Jump Location
Figure 6

(a) FoM as function of fan speed. (b) FoM as function of fin height. For the given power dissipation and cooling architecture, an optimal thermal resistance value exists for maximum FoM.

Grahic Jump Location
Figure 7

Trade-offs between thermal and exergetic resistance for various heat sink designs

Grahic Jump Location
Figure 8

Impact of increasing die area on package thermal and exergetic resistances

Grahic Jump Location
Figure 9

Assumed power dissipation map for a 100-W single-core chip. The maximum heat flux is about three times that of the dual-core case.

Grahic Jump Location
Figure 10

Loss in package performance due to nonuniformity of power dissipation. Further improvements in performance beyond the measured 98.5MIPS∕W will require improved processor architecture (larger MIPS) or an improved cooling solution (lower exergy loss).

Grahic Jump Location
Figure 11

Impact of power dissipation on package FoM. The optimal FoM will be the appropriate compromise between processor performance (in MIPS, assumed to be proportional to total power dissipation) and thermodynamic performance (as measured by exergy loss).

Grahic Jump Location
Figure 12

Evaluating impact of nonuniform input on package performance

Tables

Errata

Discussions

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In