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RESEARCH PAPERS

A Numerical Analysis of the Thermal Performance of Single Sided and Back-to-Back Tape Ball Grid Array Packages

[+] Author and Article Information
Sandeep S. Tonapi

 GE Global Research Center, Niskayuna, New York 12309tonapi@research.ge.com

Sanjeev B. Sathe

 Advanced Semiconductor Engineering, Santa Clara, California 95054

Bahgat G. Sammakia, K. Srihari

Thomas J. Watson School of Engineering and Applied Science, State University of New York at Binghamton, Binghamton, New York 13902-6000

J. Electron. Packag 128(4), 305-310 (Feb 10, 2006) (6 pages) doi:10.1115/1.2351891 History: Received July 28, 2003; Revised February 10, 2006

This paper presents the results of a comprehensive numerical study of the thermal performance of Tape Ball Grid Array package mounted on one side of a printed circuit board as well as packages mounted in back-to-back and offset configurations. A cover plate is attached to the back side of the chips to enhance heat transfer from the module. The assembled organic carrier is placed in a vertical channel. A conjugate heat transfer model is used which accounts for conduction in the packages and the card and convection in the surrounding air. The effect of location of the modules on a card with zero, one and two power planes is evaluated for thermal performance. Heat dissipation is studied for forced convection (2, 1, and 0.5ms). Comparison is made for single sided and back-to-back cases.

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Copyright © 2006 by American Society of Mechanical Engineers
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References

Figures

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Figure 4

Temperature distribution along the card center line when the module is placed at location 1, for an incoming airflow velocity of 2m∕s

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Figure 5

Temperature distribution along the card center line when the module is placed at location 2, for an incoming airflow velocity of 2m∕s

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Figure 6

Temperature distribution along the card center line when the module is placed at location 3, for an incoming airflow velocity of 2m∕s

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Figure 7

Energy fractions from the top of the module, bottom of the card, and top of the card surface for an incoming airflow velocity of 2m∕s

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Figure 8

Peak temperatures as a function of the velocity of the incoming air at the different locations for two power planes

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Figure 9

Peak temperatures as a function of the velocity of the incoming air at the different locations for one power plane

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Figure 10

Peak temperatures as a function of the velocity of the incoming air at the different locations for zero power planes

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Figure 11

Peak temperatures as a function of the velocity of the incoming air at the different locations for two power planes

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Figure 12

Peak temperatures as a function of the velocity of the incoming air at the different locations for zero power planes

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Figure 13

Temperature distribution along the card center line when the module is placed at location 2 for a case with two power planes

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Figure 3

Chip junction temperature as a function of location of the module for zero, one, and two power planes and for an incoming airflow velocity of 0.5m∕s

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Figure 2

Location of the modules on the card

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Figure 1

Schematic of the TBGA package

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