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RESEARCH PAPERS

Transient Thermal Analysis for Board-Level Chip-Scale Packages Subjected to Coupled Power and Thermal Cycling Test Conditions

[+] Author and Article Information
Tong Hong Wang1

Stress-Reliability Lab, Advanced Semiconductor Engineering, Inc., 26 Chin 3rd Rd., Nantze Export Processing Zone, 811 Nantze, Kaohsiung, Taiwan

Chang-Chi Lee

Thermal Lab, Advanced Semiconductor Engineering, Inc., 26 Chin 3rd Rd., Nantze Export Processing Zone, 811 Nantze, Kaohsiung, Taiwan

Yi-Shao Lai

Stress-Reliability Lab, Advanced Semiconductor Engineering, Inc., 26 Chin 3rd Rd., Nantze Export Processing Zone, 811 Nantze, Kaohsiung, Taiwan

Yu-Cheng Lin2

Department of Engineering Science, National Cheng Kung University, 1 Ta-Hsueh Rd., 701 Tainan, Taiwanyuclin@mail.ncku.edu.tw

1

Also at: Department of Engineering Science, National Cheng Kung University, 1 Ta-Hsueh Rd., 701 Tainan, Taiwan.

2

Corresponding author.

J. Electron. Packag 128(3), 281-284 (Oct 07, 2005) (4 pages) doi:10.1115/1.2229229 History: Received July 18, 2005; Revised October 07, 2005

In this work, thermal characteristics of a board-level chip-scale package, subjected to coupled power and thermal cycling test conditions defined by JEDEC, are investigated through the transient thermal analysis. Tabular boundary conditions are utilized to deal with time-varying thermal boundary conditions brought by thermal cycling. It is obvious from the analysis that the presence of power cycling leads to a significant deviation of the junction temperature from the thermal cycling profile. However, for components away from the die, the deviation is insignificant. Moreover, for low-power applications, temperature histories from coupled power and thermal cycling are approximately linear combinations of temperature histories from pure power cycling and the ones from pure thermal cycling.

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Copyright © 2006 by American Society of Mechanical Engineers
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References

Figures

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Figure 1

Layout of solder joints (unit: mm) and modeling region

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Figure 2

Eighth symmetry finite element model

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Figure 3

Closeup view of the finite element model around the die: (a) Entire history and (b) initial 2s

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Figure 4

Temperature histories of 1W and 5min power dissipation at 25°C, calculated using different time steps

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Figure 5

Temperature histories for Cell A

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Figure 6

Temperature histories for Cell B

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Figure 7

Temperature histories for Cell C

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Figure 8

Temperature histories for Cell D

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