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RESEARCH PAPERS

Discussion on the Reliability Issues of Solder-Bump and Direct-Solder Bonded Power Device Packages Having Double-Sided Cooling Capability

[+] Author and Article Information
John G. Bai, Jesus N. Calata, Guo-Quan Lu

Center for Power Electronics Systems and Department of Materials Science and Engineering,  Virginia Polytechnic Institute and State University, Blacksburg, VA 24061

J. Electron. Packag 128(3), 208-214 (Aug 26, 2005) (7 pages) doi:10.1115/1.2229218 History: Received January 03, 2005; Revised August 26, 2005

Power device packages with solder-bump (SB) and direct-solder (DS) interconnections were fabricated and some of their thermomechanical reliability issues were discussed based on both thermal cycling experiment and finite element analysis (FEA). The SB interconnection shows superior reliability over the DS interconnection in the thermal cycling experiment because the mismatched coefficient of thermal expansion leads to smaller stresses at the SB interconnection under the same temperature changes. On the other hand, FEA results show that the DS package has significantly lower operating temperatures under the same double-sided cooling condition. After considering the operating temperature difference, the DS package was shown to be superior over the SB package in the power cycling analysis.

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Copyright © 2006 by American Society of Mechanical Engineers
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Figures

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Figure 1

(a) A SB package with the source/gate of the power MOSFET device attached to the top DBC substrate via six 1-mm high solder-bumps, (b) a DS package with the source/gate of the device attached to the top DBC substrates via 100μm solder layers. Both 10× magnification.

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Figure 2

Temperature profiles for the thermal cycling experiment. Solid line: experimental temperature profile; Squares: temperature datum inputs for the thermal cycling FEA simulation.

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Figure 3

The thermal FEA models for (a) the SB package and (b) the DS package

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Figure 4

Cracks at the solder-silicon interfaces in a failed SB package (a) and those in a failed DS package (b) after 875 thermal cycles

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Figure 5

SAM images of the SB interconnections in a failed SB package taken after 875 thermal cycles: (a) at the solder/power device interface and (b) at the solder/DBC copper interface

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Figure 6

SAM images of the DS interconnection in a failed DS package taken after 875 thermal cycles: (a) at the solder/power device interface and (b) at the solder/DBC copper interface

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Figure 7

Thermal FEA temperature distribution results of (a) the SB and (b) the DS packages under the same operation and double-sided cooling conditions

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Figure 8

The finite element models of the SB (a) and DS (b) packages used in the transient thermomechanical analysis to simulate both thermal and power cycling experiment

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Figure 9

The average inelastic strain energy density accumulation at the corner elements of the SB (a) and DS (b) interconnections, respectively, during the first three thermal cycles

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Figure 10

Temperature profiles for power cycling simulation. Solid line for the SB package and dashed line for the DS package.

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Figure 11

The average inelastic strain energy density accumulation at the corner elements of the SB (a) and DS (b) interconnections, respectively, during the first five power cycles

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