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RESEARCH PAPERS

Thermal Phenomena in Nanoscale Transistors

[+] Author and Article Information
Eric Pop

Department of Electrical Engineering, Stanford University, Stanford, CA 94305

Kenneth E. Goodson

Department of Mechanical Engineering, Stanford University, Stanford, CA 94305goodson@stanford.edu

J. Electron. Packag 128(2), 102-108 (Dec 14, 2006) (7 pages) doi:10.1115/1.2188950 History: Received January 21, 2005; Revised December 14, 2006

As CMOS transistor gate lengths are scaled below 45nm, thermal device design is becoming an important part of microprocessor engineering. Decreasing dimensions lead to nanometer-scale hot spots in the drain region of the device, which may increase the drain series and source injection electrical resistances. Such trends are accelerated with the introduction of novel materials and nontraditional transistor geometries, like ultrathin body, surround-gate, or nanowire devices, which impede heat conduction. Thermal analysis is complicated by subcontinuum phenomenan including ballistic electron transport, which reshapes the hot spot region compared with classical diffusion theory predictions. Ballistic phonon transport from the hot spot and between material boundaries impedes conduction cooling. The increased surface to volume ratio of novel transistor designs also leads to a larger contribution from material boundary thermal resistance. In this paper we survey trends in transistor geometries and materials, from bulk silicon to carbon nanotubes, along with their implications for the thermal design of electronic systems.

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Copyright © 2004 by IEEE
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Figures

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Figure 1

Trends of on-chip power density for the past 10+ years. Note the vertical axis is logarithmic and the horizontal one (years) is linear. By comparison, typical power densities for a hot plate and a rocket nozzle are listed, while the surface of the sun puts out approximately 7000W∕cm2. The solid line marks an exponential trend. (Data compiled by F. Labonte, Stanford.)

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Figure 2

False-color Transmission Electron Microscopy (TEM) cross-section of a future-generation strained silicon-on-insulator (SSOI) transistor. Image courtesy IBM.

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Figure 5

Evolution of transistor designs from traditional bulk silicon (a) to (strained) silicon or germanium on insulator (b), to multiple-gate or FinFET devices (c). Non-traditional device designs like (b) and (c) introduce more complicated geometries and lower thermal conductivity materials, making heat removal more difficult. The gate length (currently near 50nm) is expected to be scaled to the 10nm range, while the semiconductor film and “fin” thickness of (b) and (c), respectively, are approximately one third to one half the gate length. Figure (c) is from the technology roadmap (ITRS) (1).

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Figure 3

Phonon dispersion in the (100) direction of silicon (a) and computed net (emission minus absorption) phonons generated by Joule heating (b). The symbols in (a) are from neutron scattering data and the lines are a quadratic fit (14). Solid lines are for longitudinal, and dashed lines are for transverse phonons. Optical modes are above and acoustic modes have energies below approximately 50meV, respectively. Note the vertical axes are matched (E=ℏω) to facilitate comparison of the dispersion and generated modes.

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Figure 4

Snapshot of electron transport in a future-generation thin-body silicon-on-insulator (SOI) device simulated with the Monte Carlo code MONET (13,15). The color scale is the electron energy in eV and the device dimensions are in nm.

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Figure 6

Estimated reduction in silicon and germanium thin film thermal conductivity due to phonon boundary scattering alone (i.e., no confinement). Thin silicon films suffer from a stronger reduction in thermal conductivity (vs germanium) due to the longer bulk silicon phonon mean free path (30).

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Figure 7

Thin film transistor thermal resistance model (also see Fig. 5). The dark gray areas represent the metalized gate and contacts, the light gray is the surrounding oxide insulator (21,30).

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Figure 8

Suspended silicon nanowire field effect device fabricated with electron beam lithography and a buffered HF underetch (40). The cross section of the wire is 23×80nm. The confined dimensions significantly alter both current and heat transport through the wire.

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Figure 9

Current-voltage characteristics of a 3μm long metallic single-wall carbon nanotube up to breakdown by oxidation (burning) in air, when the middle of the SWNT reaches about 600°C at 15V bias. The data (symbols) and inset (AFM image showing place of breakdown) are from Ref. 43. The model (solid line) is described in Ref. 47.

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