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RESEARCH PAPERS

Board Level Drop Impact—Fundamental and Parametric Analysis

[+] Author and Article Information
E. H. Wong

 University of Sydney, Institute of Microelectronics, 11 Science Park Road, Science Park 2, S117685 Singaporeeehua@ime.a-star.edu.sg

Y-W Mai

University of Sydney

S. K. Seah

Institute of Microelectronics

J. Electron. Packag 127(4), 496-502 (Mar 30, 2005) (7 pages) doi:10.1115/1.2065747 History: Received November 05, 2004; Revised March 30, 2005

A fundamental understanding of the dynamics of the PCB assembly when subjected to a half-sine acceleration has also been obtained through analyzing the PCB as a spring mass system, a beam, and a plate, respectively. The magnitude of stresses in solder interconnection due to flexing of the PCB is two orders higher than the magnitude of the stresses induced by acceleration and inertia loading the IC package. By ignoring the inertia loading, computational effort to evaluate the interconnection stresses due to PCB flexing can be reduced significantly via a two-step dynamic-static analysis. The dynamic analysis is first performed to evaluate the PCB bending moment adjacent the package, and is followed by a static analysis where the PCB bending moment is applied around the package. Parametric studies performed suggest a fundamental difference in designing for drop impact and designing for temperature cycling. The well-known design rules for temperature cycling—minimizing package length and maximizing interconnection standoff—does not work for drop impact. Instead, drop impact reliability can be enhanced by increasing the interconnection diameter, reducing the modulus of the interconnection materials, reducing the span of the PCB, or using either a very thin or a very thick PCB.

Copyright © 2005 by American Society of Mechanical Engineers
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References

Figures

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Figure 1

A typical drop impact test setup

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Figure 2

Board level drop impact modeled as two spring-mass systems

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Figure 17

Parametric analysis on peak σy stress with respect to PCB length (span)

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Figure 16

Parametric analysis on peak σy stress with respect to PCB thickness

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Figure 15

Parametric analysis on peak σy stress with respect to PCB modulus

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Figure 14

Parametric analysis on peak σy stress with respect to package length and interconnection pitch

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Figure 13

Effects of interconnection diameter on (a) σy stress profile along the PCB end of the outermost interconnection; (b) σy stress along all interconnections at the PCB end

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Figure 12

Effect of interconnection length on (a) σy-stress profile along the PCB end of the outermost interconnection; (b) σy-stress contour along the PCB end of all interconnections

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Figure 11

Parametric analysis for (a) peak σy-stress with respect to the modulus and thickness of package and the modulus of interconnection; (b) individual stress components with respect to package modulus

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Figure 10

Static σy stress contours and profiles in interconnections

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Figure 9

Static stresses in interconnections evaluated with FE beam analysis: (a) PCB end; (b) package end

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Figure 5

Bending moment and acceleration response spectrum for (a) beam model and (b) plate model

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Figure 4

Beam model and the coordinate system for the PCB

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Figure 3

Spring-mass model for the PCB

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Figure 8

Axial stress in interconnections subjected to a static PCB bending moment

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Figure 7

The beam-on-foundation model for the board assembly

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Figure 6

Time response of bending moment and acceleration at the midpoint of a beam using parameters in Table 1

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