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RESEARCH PAPERS

Hygrothermal Cracking Analysis of Plastic IC Package

[+] Author and Article Information
Ji Hyuck Yang

 Hyundai Motor Company, 772-1, Jangduk-dong, Whasung-si, Gyunggi-do, 445-706, Korea (Republic)

Kang Yong Lee

 Department of Mechanical Engineering, Yonsei University SinchonDong, SeodaemoonGu, Seoul 120-749, KoreaKYL2813@yahoo.co.kr

J. Electron. Packag 127(2), 164-171 (Jun 08, 2004) (8 pages) doi:10.1115/1.1870016 History: Received May 16, 2004; Revised May 31, 2004; Accepted June 08, 2004

The purposes of the paper are to consider the failure phenomenon by delamination and crack when the encapsulant of plastic IC package under hygrothermal loading in the IR soldering process shows elastic and viscoelastic behaviors and to suggest the optimum design by the approaches of stress analysis and fracture mechanics. The model for analysis is the plastic Small Outline J-lead package with a dimpled diepad. On the package without a crack, the stress analysis is done and the possibility of delamination is considered. For the model fully delaminated between the chip and the dimpled diepad, J-integrals in low temperature and C(t)-integrals in high temperature are calculated for the various design variables and the fracture integrity is discussed. Finally, the optimal values of design variables to depress the delamination and crack growth in the plastic IC package are obtained.

Copyright © 2005 by American Society of Mechanical Engineers
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Figures

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Figure 1

SOJ plastic package

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Figure 2

Measured temperature profiles

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Figure 3

Stress concentration points

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Figure 4

Variation of von Mises equivalent stress during reflow soldering process under thermal loading

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Figure 5

Moisture absorption model

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Change of vapor pressure with contamination factor values

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Figure 7

Configuration of delamination model

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Crack tip modeling

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FE crack modeling

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Figure 11

Changes of J- and C(t)-integrals for the crack direction during reflow soldering process

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Figure 12

Verification of the path-independence of J- and C(t)-integrals during reflow soldering process

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Figure 13

Changes of J- and C(t)-integrals with thickness of EMC and contamination factor

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Changes of maximum J- and C(t)-integrals with thickness of EMC during reflow soldering process

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Figure 15

Comparison of J- and C(t)-integrals for packages with flat and dimpled diepads under reflow soldering process

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