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RESEARCH PAPERS

Development of Novel Filler Technology for No-Flow and Wafer Level Underfill Materials

[+] Author and Article Information
Slawomir Rubinsztajn, Donald Buckley, John Campbell, David Esler, Eric Fiveland, Ananth Prabhakumar, Donna Sherman, Sandeep Tonapi

General Electric Company Global Research Center 1 Research Circle, Niskayuna, NY 12309

J. Electron. Packag 127(2), 77-85 (Jun 03, 2005) (9 pages) doi:10.1115/1.1846067 History: Received January 13, 2004; Revised June 23, 2004; Online June 03, 2005
Copyright © 2005 by ASME
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References

Lau, J. H., 2000, Low Cost Flip Chip Technology for DCA, WLSCP and PBGA Assemblies, McGraw–Hill, New York.
Thorpe, R., Baldwin, D. F., and McGovern, L. P., “High Throughput Flip Chip Processing and Reliability Analysis Using No-Flow Underfills,” Proc. 49th ECTC, San Diego, p. 419.
Shi, S. H., Yamashita, T., and Wong, C. P., 1999, “Development of a Wafer Level Compressive Flow Underfill Process and its Required Materials,” Proc. 49th Electronic Components and Technology Conference, San Diego, CA, pp. 961–966.
Gamota,  D., and Melton,  C., 1998, “Materials to Integrate the Solder Reflow and Underfill Encapsulation Processes for Flip Chip on Board Assembly,” IEEE Trans. Compon., Packag. Manuf. Technol., Part C, 21(1), pp. 57–65.
Liu, J., Kraszewski, R., Lin, X., Wong, L., Goh, S. H., and Allen, J., 2001, “New Developments in Single Pass Reflow Encapsulant for Flip Chip Application,” Int. Symposium on Advanced Packaging Materials, pp. 74–79.
Zhang Z., and Wong, C. P., 2002, “Double Layer No-flow Underfill Materials and Process,” Proc. 52nd Electronic Components and Technology Conference, San Diego, CA, pp. 199–205.
Gross, K., Hackett, S., Larkey, D., Schultz, W., and Thompson, W., 2002, “New Materials for High Performance No-Flow Underfill Materials,” Proc. IMAPS, Denver, pp. 234–238.
Gross, K., Hackett, S., Schultz, W., Thompson, W., Zhang, Z., Fan, L., and Wong, C. P., 2003, “Nanocomposite Underfills for Flip Chip Applications,” 53rd Electronic Components and Technology Conference, New Orleans, pp. 951–956.
Nguyen, L., Nguyen, H., Negasi, A., Tong, Q., and Hong, S. H., 2002, “Wafer Level Underfill-Processing and Reliability,” Proc. SEMICON West 2002, San Jose, CA, pp. 53–62.
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Iler. R., 1979, The Chemistry of Silica, Wiley, New York.
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Suratwala,  T. I., Hanna,  M. L., Miller,  E. L., Whitman,  P. K., Thomas,  I. M., Ehrmann,  P. R., Maxwell,  R. S., and Burnham,  A. K., 2003, J. Non-Cryst. Solids, 316, pp. 349–363.
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LeGall, C. A., Qu, J., and McDowell, D. L., 1997, “Some Mechanics Issues Related to the Thermomechanical Reliability of Flip Chip Dca With Underfill Encapsulation,” in Application of Fracture Mechanics in Electronic Packaging (Proceedings of the ASME International Mechanical Engineering Congress and Exposition, November 16–21, 1997, Dallas, TX), W. T. Chem and D. T. Read, eds., ASME, New York, pp. 85–95.
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Figures

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TEM of the thin film of the cured dispersion of FCS in epoxy resin
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Example of solder wetting and coalescence for experimental epoxy resins: (a) epoxy filled with 5μm fused silicon (b) unfilled epoxy (c) epoxy filled with nanosized FCS. Test done by heating to reflow temperature a covered glass slide containing resin and 25 mil eutectic solder balls.
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SEM images of the cross section of the sample A (Fig. 2).
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Effect of catalyst level on the cure profile of experimental NFU materials. Nonisothermal DSC at heating rate of 30°C/min.
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DMA data for experimental NFU-1A
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a-Volcano reflow profile; b-soak reflow profile
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x-ray analysis of the PB10 test die assembled with NFU (a) Commercial grade (b) NFU-1B
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Top view of a flip chip assembled with nano-filled NFU-1B
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C-SAM images of flip chips assembled with (a) commercial grade and (b) experimental grade NFU-1B
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Center dot dispense and modified line dispense patterns used in NFU assembly
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Cross-sectional view of the PB8 test die assembled with experimental NFU that was not optimized
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Cross-sectional view of the PB8 test die assembled with experimental NFU-1B
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C-SAM images of flip chips assembled with experimental nanofilled underfill GE-1B (a)-before being subjected to thermal shock. (b) After 500 cycles of thermal shock, (c) after 1000 cycles of thermal shock.
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Transparency of 6 μm films of experimental GE WLU resins.
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View of saw streets through B-stage underfill layer (a) before dice (b) after dicing operation
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Solder bump collapse after reflow (16A-flux only, 16B flux+GE-WLU)

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