A New Wafer Level Packaging Approach: Encapsulation, Metallization and Laser Structuring for Advanced System in Package Manufacturing

[+] Author and Article Information
K.-F. Becker, T. Braun, A. Neumann, A. Ostmann, E. Coko, M. Koch, V. Bader, R. Aschenbrenner, H. Reichl

BeCAP—Berlin Center for Advanced Packaging, Fraunhofer Institute for Reliability and Microintegration—TU Berlin Microperipherics Center, Gustav-Meyer-Allee 25, D-13355 Berlin, Germany

Phone: +49-30/464 03 242, Fax: +49-30/464 03 254

J. Electron. Packag 127(1), 1-6 (Mar 21, 2005) (6 pages) doi:10.1115/1.1846058 History: Received January 06, 2004; Revised June 24, 2004; Online March 21, 2005
Copyright © 2005 by ASME
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Schematics of a WL package generated using duromer MID processes
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Schematics of the process flow for WLP/MID stackable package generation for a single chip device. The processing at wafer level is also possible.
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Process options for Duromer MID. Left: Schematic of the transfer molding process for a WL SiP module; arrows indicate additional components attached to the active side of the IC. Right: Batch processing for volume production of Duromer MID modules.
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Surface topography of a typical WL EMC after molding
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Surface topography of typical WL EMC after etching in overview (left) and in detail (right), where submicron particles cover larger particles
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AFM analysis of the surface topography of a typical WL EMC prior to (top) and after etching (bottom) showing increased micro roughness for improved mechanical adhesion
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Surface topography of a typical WL EMC after metallization
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SEM images of structured metallization on encapsulant with vias; detail of metallized via from the top (left) and x-sectioned (right)
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Optical microscopic image of a package bottom side with solder balls
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Image of a 3D package stack realized by WLP/MID technology
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RF antenna for a frequency of 13.56 MHz realized in duromer MID technology




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