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RESEARCH PAPER

Effect of Underfill Entrapment on the Reliability of Flip-Chip Solder Joint

[+] Author and Article Information
Y. C. Chan, M. O. Alam, K. C. Hung, H. Lu, C. Bailey

EPA Centre, Department of Electronic Engineering, City University of Hong Kong, Hong Kong, ChinaSchool of Computing and Mathematical Science, The University of Greenwich, Greenwich, UK

J. Electron. Packag 126(4), 541-545 (Jan 24, 2005) (5 pages) doi:10.1115/1.1756590 History: Received May 01, 2003; Revised April 01, 2004; Online January 24, 2005
Copyright © 2004 by ASME
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References

Figures

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Measured reflow profile for no-flow flip chip package
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Thermal shock conditions
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Optical micrograph showing trapping of thick layer of no-flow underfill after reflow
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Optical micrograph showing the cross-section of the no-flow flip chip solder joint, which presents a good bonding between solder bump and substrate pad
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Accumulated creep strain distribution in solder (a) no trapped underfill and (b) with trapped underfill. Only solder material is shown.
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A model with trapped underfill. The center is filled with solder and therefore the joint still has good electric connection.
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SAM picture of no-flow flip chip sample. Few voids (white spots) inside the underfill layer are observed.
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Schematic diagram of no-flow flip chip bonding with (a) perfect interconnection, (b) underfill entrapment at one edge, both edges or surrounding the periphery of the joint, and (c) no interconnection due to occurrence of underfill layer between solder and pad
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Optical micrograph showing the cross-section of the no-flow flip chip solder joint, which presents a good solder joint interconnection but with underfill entrapment between solder and substrate pad

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