Development of Compact Models for Electronics Cooling: Using the Multigrid Operator to Generate Reduced-Order Description of Devices

[+] Author and Article Information
Prabhu Sathyamurthy, Manoj Nagulapally, Rajesh Nair

Fluent Inc., 10 Cavendish Court, Lebanon, NH 03766

J. Electron. Packag 126(4), 472-476 (Jan 24, 2005) (5 pages) doi:10.1115/1.1827263 History: Received April 28, 2004; Revised May 04, 2004; Online January 24, 2005
Copyright © 2004 by ASME
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Grahic Jump Location
Network model for a typical 2-D chip package
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Schematic of the FBGA package
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ACE network topology of the FBGA
Grahic Jump Location
Transient response of a 14-node ACE network compared to the detailed FBGA




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