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RESEARCH PAPER

The Thermoelastic Analysis of Chip-Substrate System

[+] Author and Article Information
Linzhi Wu

School of Astronautics, Harbin Institute of Technology, Harbin 150001, P.R. China

J. Electron. Packag 126(3), 325-332 (Oct 06, 2004) (8 pages) doi:10.1115/1.1772413 History: Received May 01, 2003; Revised January 01, 2004; Online October 06, 2004
Copyright © 2004 by ASME
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References

Chen,  W. T., and Nelson,  C. W., 1979, “Thermal Stress in Bonded Joints,” IBM J. Res. Dev., 23, pp. 178–188.
Suhir,  E., 1986, “Stresses in Bi-Metal Thermostats,” ASME J. Appl. Mech., 53, pp. 657–660.
Suhir,  E., 1989, “Interfacial Stresses in Bimetal Thermostats,” ASME J. Appl. Mech., 56, pp. 595–600.
Kuo,  A. Y., 1989, “Thermal Stresses at the Edge of a Bimetallic Thermostat,” ASME J. Appl. Mech., 56, pp. 585–589.
Lee,  M., and Jasiuk,  L., 1991, “Asymptotic Expansions for the Thermal Stresses in Bonded Semi-Infinite Bimaterial Strips,” ASME J. Electron. Packag., 113, pp. 173–177.
Yin,  W. L., 1991, “Thermal Stresses and Free-Edge Effects in Laminated Beams: a Variational Approach Using Stress Functions,” ASME J. Electron. Packag., 113, pp. 68–75.
Suhir, E., ed., 1995, Global and Local Thermal Mismatch Stresses in an Elongated Bi-Material Assembly Adhesively Bonded at the Ends: Structural Analysis in Microelectronic and Fiber-Optic Structures, ASME Press, New York, pp. 101–105.
Jiang,  Z. Q., Huang,  Y., and Chandra,  A., 1997, “Thermal Stresses in Layered Electronic Assemblies,” ASME J. Electron. Packag., 119, pp. 127–132.
Xie,  W. D., and Sitaraman,  S. K., 2000, “Interfacial Thermal Stress Analysis of Anisotropic Multi-Layered Electronic Packaging Structures,” ASME J. Electron. Packag., 122, pp. 61–66.
Wang,  K. P., Huang,  Y. Y., Chandra,  A., and Hu,  K. X., 2000, “Interfacial Shear Stress, Peeling Stress, and Die Cracking Stress in Trilayer Electronic Assemblies,” IEEE Trans. Compon., Packag. Manuf. Technol., Part A, 23, pp. 309–316.
Feng,  Y. Y., and Wu,  L. Z., 2001, “Analysis of Interfacial Thermal Stresses of Chip-Substrate Structure,” Int. J. Solids Struct., 38, pp. 1551–1562.
Saganuma,  K., Okamoto,  T., and Koizumi,  M., 1984, “Effect of Interlayers in Ceramic-Metal Joints With Thermal Expansion Mismatches,” J. Am. Ceram. Soc., 67, pp. C256–C257.
Blanchard,  J. P., and Watson,  R. D., 1986, “Residual Stresses in Bonded Armor Tiles for On-Vessel Fusion Components,” Nucl. Eng. Des., 4, pp. 61–66.
Gerstle, F. P., Jr., and Chambers, R. S., 1987, “Analysis of End Stresses in Glass-Metal Bi-Material Strips,” ASME WAM, Boston, Mass.
Lau,  J. H., 1989, “A Note on the Calculation of Thermal Stresses in Electronic Packaging by Finite Element Methods,” ASME J. Electron. Packag., 111, pp. 313–320.
Pionke,  C. D., and Wempner,  G., 1991, “The Various Approximations of the Bimetallic Thermostatic Strip,” ASME J. Appl. Mech., 58, pp. 1015–1020.
Jain,  S. C., 1995, “Edge-Induced Stress and Strain in Stripe Films and Substrates: A Two-Dimensional Finite Element Calculation,” J. Appl. Phys., 78, pp. 1630–1637.
Hu,  S. M., 1991, “Stress-Related Problems in Silicon Technology,” J. Appl. Phys., 50, pp. 4661–4666.
Hu,  S. M., 1979, “Film-Edge-Induced Stress in Substrates,” J. Appl. Phys., 70, pp. R53–R80.
Frost, H. F., and Ashby, M. F., 1982, Deformation Mechanism Maps, Pergamon, New York, pp. 71–74.

Figures

Grahic Jump Location
Chip-substrate structure. The dimension of the sample along the y-axis (perpendicular to the diagram) is assumed to be infinitely long.
Grahic Jump Location
Heat conduction model of the chip-substrate structure
Grahic Jump Location
The variation of stresses in the substrate at a depth of one unit from the interface along the x-axis. Solid line with Δ sign corresponds to stress component σ1z; solid line with ⊕ sign: σ1x; solid line with ○ sign: σ1xz.
Grahic Jump Location
The variation of stresses in the substrate at a depth of one unit from the interface along the x-axis. Here, l0=10,h0=1,l1=50,h1=50. Solid line with Δ sign corresponds to σ1zz; solid line with ○ sign: σ1xz; solid line with ⊕ sign: σ1xx.
Grahic Jump Location
The variation of normal stress σ1zz in the substrate at a depth 0.5 from the interface as a function of x. Δ: h1=10; ○: h1=20; ⊕: h1=50.
Grahic Jump Location
The variation of shear stress σ1xz in the substrate at a depth 0.5 from the interface as a function of x. Δ: h1=10; ○: h1=20; ⊕: h1=50.
Grahic Jump Location
The variation of normal stress σ1xx in the substrate as a function of x at a depth 0.5 from the interface. Δ: h1=10; ○: h1=20; ⊕: h1=50.
Grahic Jump Location
The variation of normal stress σ1zz in the substrate as a function of x at a depth 0.5 from the interface. h0=1,l1=50,h1=50. Δ: l0=10; ○: l0=15; ⊕: l0=20.
Grahic Jump Location
The variation of shear stress σ1xz in the substrate as a function of x at a depth 0.5 from the interface. h0=1,l1=50,h1=50. Δ: l0=10; ○: l0=15; ⊕: l0=20.
Grahic Jump Location
The variation of normal stress σ1xx in the substrate as a function of x at a depth 0.5 from the interface. h0=1,l1=50,h1=50. Δ: l0=10; ○: l0=15; ⊕: l0=20.

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