Warpage Analysis of Underfilled Wafers

[+] Author and Article Information
Hai Ding, I. Charles Ume, Cheng Zhang

School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332

J. Electron. Packag 126(2), 265-270 (Jul 08, 2004) (6 pages) doi:10.1115/1.1707036 History: Received October 01, 2001; Revised October 01, 2002; Online July 08, 2004
Copyright © 2004 by ASME
Your Session has timed out. Please sign back in to continue.


Garrou,  P., 2000, “Wafer Level Chip Scale Packaging (WL-CSP): An Overview,” IEEE Trans. Adv. Packag., 23(2), Maypp. 198–205.
Johnson, C.D., Busch, S.C., and Baldwin, D.F., 1999, “Wafer Scale Packaging Based on Underfill Applied at the Wafer Level for Low Cost Flip Chip Processing,” Proceedings of SPIE, Vol. 3830, pp. 371–375.
Shi,  S., Yamashita,  T., and Wong,  C.P., 1999, “Development of the Wafer Level Compressive-Flow Underfill Process and Its Involved Materials,” IEEE Transactions on Electronics Packaging Manufacturing, 22(4), October, pp. 274–281.
Yeh,  C.P., Ume,  I.C., Fulton,  R.E., Wyatt,  K.W., and Stafford,  J.W., 1993, “Correlation of Analytical and Experimental Approaches to Determine Thermally Induced PWB Warpage,” IEEE Trans. Compon., Hybrids, Manuf. Technol., 16(8), December, pp. 986–995.
Ume,  I.C., Martin,  T., and Gatro,  J.T., 1997, “Finite Element Analysis of PWB Warpage Due to the Solder Masking Process,” IEEE Trans. Compon., Packag. Manuf. Technol., Part A, 20(3), September, pp. 295–306.
Ume,  I.C., and Martin,  T., 1997, “Finite Element Analysis of PWB Warpage Due to Cured Solder Mask-Sensitivity Analysis,” IEEE Trans. Compon., Packag. Manuf. Technol., Part A, 20(3), September, pp. 307–316.
ANSYS, Inc., 1998, ANSYS Elements Reference, Tenth Edition.
Variyam,  M.N., Xie,  W., and Sitaraman,  S.K., 2000, “Role of Out-of-Plane Coefficient of Thermal Expansion in Electronic Packaging Modeling,” ASME J. Electron. Packag., 122(2), pp. 121–127.
Stiteler,  M., and Ume,  I.C., 1997, “System for Real-Time Measurements of Thermally Induced Warpage in a Simulated Infrared Soldering Environment,” ASME J. Electron. Packag., 119, pp. 1–7.
Christensen, R., 1996, Analysis of Variable, Design and Regression, Applied Statistical Methods, Chapman & Hall, pp. 414–431.


Grahic Jump Location
Wafer-level flip-chip process
Grahic Jump Location
Half cross-section of an underfilled wafer
Grahic Jump Location
Mesh of 3D solid element
Grahic Jump Location
Deformed shape along with undeformed line frame of Run #2
Grahic Jump Location
Residuals vs. order of the reduced model
Grahic Jump Location
Normal probability plot of the reduced model
Grahic Jump Location
Fringe pattern and surface plot of shadow moiré result of Run #2
Grahic Jump Location
A typical shadow moiré setup




Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In