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TECHNICAL PAPERS

Effects of Wafer Thinning Condition on the Roughness, Morphology and Fracture Strength of Silicon Die

[+] Author and Article Information
Neil McLellan, Nelson Fan, Shilai Liu, Kim Lau, Jingshen Wu

Department of Package Development and Engineering, ASAT Ltd. Tsuen Wan, NT, Hong KongDepartment of Mechanical Engineering, Hong Kong University of Science & Technology, Kowloon, Hong Kong

J. Electron. Packag 126(1), 110-114 (Apr 30, 2004) (5 pages) doi:10.1115/1.1647123 History: Received March 01, 2003; Online April 30, 2004
Copyright © 2004 by ASME
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References

Figures

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Sampling locations and scratch patterns
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Schematic of the three-point bending test of samples with different scratch pattern: (a) vertical, (b) horizontal.
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(a)–(f ) 3-D micrographs of the morphology of chip surfaces after different thinning processes (scanned area: 62×81 μm2).
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Roughness (Ra) vs. wafer thinning conditions
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Fracture strength vs. surface scratch pattern
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(a) & (b) Fracture strength vs. grit sizes of coarse/fine grinding wheels
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Fracture strength vs. fine-grinding depth
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Fracture strength vs. various polishing techniques
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3-D micrograph of the morphology of chip surface after dry polishing process (scanned area: 62×81 μm2).
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Effects of backside surface thinning methods on die fracture strength.
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Typical serious flaws for different surface: (a) Mechanical grinding, (b) Plasma etching (scanned area: 62×81 μm2).
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Illustration of plasma etching effect on flaw shape.

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