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TECHNICAL PAPERS

Parameterized Modeling of Thermomechanical Reliability for CSP Assemblies

[+] Author and Article Information
Bart Vandevelde, Eric Beyne

IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

Kouchi (G.Q.) Zhang, Jo Caers

CFT/Philips, P.O. Box 218, 5600 MD Eindhoven, The Netherlands

Dirk Vandepitte, Martine Baelmans

Catholic University of Leuven, Celestijnenlaan 300A, B-3001 Leuven, Belgium

J. Electron. Packag 125(4), 498-505 (Dec 15, 2003) (8 pages) doi:10.1115/1.1604150 History: Received November 01, 2002; Online December 15, 2003
Copyright © 2003 by ASME
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References

Figures

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Solder joint cracks due to thermal fatigue are always found near the interface with the chip, and always in one of the four corner joints
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Three-dimensional finite element model for 5×4 Philips CSP mounted on a PCB
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Distribution of accumulated equivalent creep strains in the solder joint (after three cycles). The largest strains are found in the corner joint, near chip side.
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Correlation between the inelastic strain and number of temperature cycles to 50% failures (a result of thermal cycling tests)
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Accuracy of the reliability estimation by FEM (the different test configurations are estimated using a specific empirical model that is derived without using the particular test case)
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Scatter plot, showing the accuracy of the RSM
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Contribution plot for N50%. If the coefficient is negative (bar at the left), an increase of that coefficient results in a decrease of the output parameter, which is N50%.
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Plastic strains in the damage area for the solder joints located on the diagonal. Different CSP sizes are considered.
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Validation of simulation results by N50% test results, for different area array configurations for the CSP assemblies
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Maximum induced plastic strains for n×n CSP with peripheral respectively area array pad configuration
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Transition from peripheral to area array (by increasing the number of rows at the perimeter)
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Simulation results for different n1×n2 pad configuration providing the same number of I/O configurations
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Histogram of 77 simulation results
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Scatter plot for the six-parameter analysis
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Contribution plot for the six-parameter DOE analysis
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Schematic drawing of the 5×4 area array CSP solder connection

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