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TECHNICAL PAPERS

Prediction of Thermal Performance of Wire-Bonded Plastic Ball Grid Array Package for Underhood Automotive Applications

[+] Author and Article Information
K. Ramakrishna

CMOS Platform Device Development, Digital DNA™ Laboratories, Semiconductor Products Sector, Motorola, Inc., 3501 Ed Bluestein Boulevard, Austin, TX 78721, USAe-mail: k.ramakrishna@motorola.com

J. R. Trent

Transportation Products Systems Group, Semiconductor Products Sector, Motorola, Inc., 6501 William Cannon Drive West, Austin, TX 78735-8598, USA

J. Electron. Packag 125(3), 447-455 (Sep 17, 2003) (9 pages) doi:10.1115/1.1602710 History: Received August 01, 2001; Revised October 01, 2002; Online September 17, 2003
Copyright © 2003 by ASME
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References

Figures

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Cross-section of a three-chip four layer WB-PBGA package showing dies, package substrate, and molding compound
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Schematic diagram of the assembly of a three-chip WB-PBGA package used in the package level CFD analysis
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Cross section of four layer WB-PBGA substrate used in the package level thermal analysis. Total thickness of the substrate is 0.6 mm and the thickness of individual solid copper planes is 0.0356 mm.
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Layup of 100×100×1.52 mm 2s2p FR4 PWB used in the package level thermal analysis of a three-chip WB-PBGA package
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CFD model of stand-alone three-chip WB-PBGA package. (A) shows overall CFD model including the free surfaces far in the ambient. (B) shows details of the package. The outer box in (A) represents the free surfaces, which are located “far” in the ambient. These surfaces are located 570 mm above the top of the molding compound, and 25 mm in the front, back, and below it.
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Velocity vectors over the molding compound in a plane passing through the middle of U1 die (in the xz plane at y=76.288 mm). Base case. The scale shows velocity in m/s.
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Variation of normal velocity component, uz, along the length of the three-chip four layer WB-PBGA package in a plane passing through the middle of the U1 die. Vertical (z) location of 28.567 mm is immediately above the molding compound surface and z=13.326 mm is approximately 11.7 mm below the bottom surface of the PWB.
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Temperature distribution in a horizontal plane in a four-layer WB-PBGA package for Ta=125°C,kda=3.7 W/(m K), ε=0.8, kMC=0.67 W/(m K),ksub=2.27 W/(m K). The horizontal plane (z=27.792 mm) in this figure passes through the top surface of U1. The top surfaces of the dies are located at: z=27.901 mm for U1,z=27.981 mm for U2, and z=27.684 mm for U3.
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Temperature distribution in a surface immediately above the top surface of the molding compound for Ta=125°C,kda=3.7 W/(m K), ε=0.8, kMC=0.67 W/(m K),ksub=2.27 W/(m K). Location is z=28.567 mm. Top surface of the molding compound surface is at z=28.347 mm. The die labels indicate their location inside the molding compound.
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Variation of junction and case temperature rise, above ambient, in a three-chip four layer WB-PBGA package as a function of ambient temperature Ta for kda=3.7 W/(m K), ε=0.8, kMC=0.67 W/(m K),ksub=2.27 W/(m K)
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Variation of ΔT, junction, and case temperature rise above ambient, in a three-chip four layer WB-PBGA package as a function of total hemispherical emissivity ε of the molding compound and the PWB for Ta=125°C,kda=3.7 W/(m K),kMC=0.67 W/(m K),ksub=2.27 W/(m K)
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Variation of ΔT, junction, and case temperature rise above ambient, in a three-chip four layer WB-PBGA package as a function of the thermal conductivity of the die attach material for Ta=125°C, ε=0.8, kMC=0.67 W/(m K),ksub=2.27 W/(m K)
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Variation of ΔT, junction, and case temperature rise above ambient, in a three-chip four layer WB-PBGA package as a function of the thermal conductivity of the molding compound for Ta=125°C, ε=0.8, kda=3.7 W/(m K),ksub=2.27 W/(m K)
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Variation ΔT, junction, and case temperature rise above ambient, in a three-chip four layer WB-PBGA package as a function of the thermal conductivity of the substrate for Ta=125°C, ε=0.8, kda=3.7 W/(m K),kMC=0.67 W/(m K)

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