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TECHNICAL PAPERS

Thermo-Viscoelastic Analysis of Deflection in CSP Electronic Device Packages

[+] Author and Article Information
Hideo Koguchi

Nagaoka University of Technology, 1603-1 Kamitomioka, Nagaoka, Niigata, 940-2188, Japane-mail: koguchi@mech.nagaokaut.ac.jp

Chie Sasaki

Matushita Electric Industrial Co., LTD. 2-7, Matsuba-cho, Kadoma, Osaka, 576-0053, Japan

Kazuto Nishida

Matushita Electric Industrial Co., LTD. 2-7, Matsuba-cho, Kadoma, Osaka, 576-0053, Japane-mail: knishida@ped.mei.co.jp

J. Electron. Packag 125(3), 414-419 (Sep 17, 2003) (6 pages) doi:10.1115/1.1602705 History: Received July 01, 2002; Online September 17, 2003
Copyright © 2003 by ASME
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References

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Figures

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Schematic view of a multi-layered stack plate
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Size of sample in experiment and an example of deformation of chip in CSP
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Boundary condition and the size of model in FEM
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Master curve of relaxation modulus for FR-4 substrate
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History of temperature during the cooling process
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Deflection of CSP with FR-4 substrate using the viscoelastic formulation
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Displacement w against the chip thickness of CSP: (a) FR-4 substrate of 0.4 mm in thickness; (b) ALIVH substrate of 0.4 mm in thickness
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Displacement w against the chip thickness of CSP with FR-4 substrate
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Displacement w against the chip thickness of CSP with ALIVH substrate

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