0
TECHNICAL PAPERS

Simulation of Void Growth in Molten Solder Bumps

[+] Author and Article Information
Ronald L. Panton, Jong W. Lee

Mechanical Engineering Department, University of Texas, Austin, TX

Lakhi Goenka, Achyuta Achari

Visteon, Electronics Technical Center, Dearborn, MI

J. Electron. Packag 125(3), 329-334 (Sep 17, 2003) (6 pages) doi:10.1115/1.1569954 History: Received April 16, 2002; Online September 17, 2003
Copyright © 2003 by ASME
Your Session has timed out. Please sign back in to continue.

References

Figures

Grahic Jump Location
Cross section of a chip assembly in reflow oven
Grahic Jump Location
Micrograph of two solder bumps (200-micron diameter) showing voids (photo by Bhattahacharya and Panton)
Grahic Jump Location
Bulk flow velocity vector pattern in a r-z plane
Grahic Jump Location
History of bubbles for the benchmark case
Grahic Jump Location
Final bubble configuration for the benchmark case; melting from top to bottom
Grahic Jump Location
Final bubble configuration for the benchmark case; melting from bottom to top

Tables

Errata

Discussions

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In