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ADDITIONAL TECHNICAL PAPERS

Measurement of Creep and Relaxation Behaviors of Wafer-Level CSP Assembly Using Moiré Interferometry

[+] Author and Article Information
Suk-Jin Ham, Soon-Bok Lee

CARE—Electronic Packaging Laboratory, Department of Mechanical Engineering, Korea Advanced Institute of Science and Technology, Science Town, Daejon, 305-701, Korea

J. Electron. Packag 125(2), 282-288 (Jun 10, 2003) (7 pages) doi:10.1115/1.1571571 History: Received May 30, 2002; Online June 10, 2003
Copyright © 2003 by ASME
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References

Kim, D. H. et al., 1999, “Electrical Performance of a Lead Frame CSP and a Wafer Level CSP for DRAM Applications,” Proc., Fourth Annual Pan Pacific Microelectronics Symposium, Kauai, HI, pp. 79–84.
Yang, H., Larson, A., Barrett, S. T., and Elenius, P., 1998, “Reliability Evaluation of Ultra CSP™ Packages,” Proc. SMTA, 5th Annual Emerging Technologies Symposium, Chandler, AZ, November 16–18, pp. 85–92.
Yang, H. et al., 2000, “Reliability Characterization in Ultra CSP™ Package Development,” IEEE 50th ECTC, Las Vegas, NV, May 21–24.
Guo,  Y., Lim,  C. K., Chen,  W. T., and Woychik,  C. G., 1993, “Solder Ball Connect (SBC) Assemblies under Thermal Loading: I. Deformation Measurement via Moiré Interferometry, and Its Interpretation,” IBM J. Res. Dev., 37, pp. 625–647.
Han,  B., and Guo,  Y., 1995, “Thermal Deformation Analysis of Various Electronic Packaging Products by Moiré and Microscopic Moiré Interferometry,” ASME J. Electron. Packag., 117, pp. 185–191.
Han, B., Caletka, D., and Guo., Y., 1995, “On The Effect of Moiré Specimen Preparation on Solder Ball Strains of Ball Grid Array Package Assembly,” Proc., 1995 SEM Spring Conference on Experimental Mechanics, Grand Rapid, MI, pp. 115–120.
Han,  B., Guo,  Y., Lim,  C. K., and Caletka,  D., 1996, “Verification of Numerical Models Used in Microelectronics Packaging Design by Interferometric Displacement Measurement Methods,” ASME J. Electron. Packag., 118, pp. 157–163.
Han,  B., 1997, “Deformation Mechanism of Two-Phase Solder Column Interconnections Using Highly Accelerated Thermal Cycling Condition: An Experimental Study,” ASME J. Electron. Packag., 119, pp. 189–196.
Han,  B., 1998, “Recent Advancements of Moiré and Microscopic Moiré Interferometry for Thermal Deformation Analyses of Microelectronics Devices,” Exp. Mech., 38(4), pp. 278–288.
Wang,  J., Qian,  Z., Zou,  D., and Liu,  S., 1998, “Creep Behavior of a Flip-Chip Package by Both FEM Modeling and Real Time Moiré Interferometry,” ASME J. Electron. Packag., 120, pp. 179–185.
Zhao, Y., Dishongh, T., Cartwright, A., and Basaran, C., 1999, “Creep Behavior of BGA Solder Joints During Thermal Cycling By Moiré Interferometry,” Advances in Electronic Packaging, EEP-Vol. 26-1, pp. 685–691.
http://www.photomechanics.com.
ABAQUS, User’s Manual, Ver. 5.8, HKS Inc.
Darveaux, R. et al., 1994, “Reliability of Ball Grid Array Solder Joints,” Ball Grid Array Technology, Chap. 13, ed., J. H. Lau, McGraw-Hill.

Figures

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Specimen for moiré interferometry study: (a) specimen cut from CSP assembly, providing cross section having 15 solder bumps; (b) cross section of the solder bump of CSP assembly
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Small-sized thermal chamber with optical windows
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Finite element model for the CSP assembly studied
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Moiré fringes and FEA simulation of the right half of a CSP assembly corresponding to the isothermal loading case from 100°C to room temperature (ΔT=−75°C): (a) U displacement field; (b) V displacement field
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Relative displacement between the chip and the board in the x direction, and the nominal shear strain in each solder bump
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U displacement fields of the corner solder bumps induced by the isothermal loading from 100°C to room temperature (ΔT=−75°C): (a) after 1 day; (b) after 60 days. The contour interval is 417 nm per fringe.
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Vertical displacement along the centerline of the chip
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Moiré fringes and FEA simulation of the right half of a CSP assembly corresponding to the thermal loading case from room temperature to 100°C (ΔT=75°C): (a) U displacement field; (b) V displacement field
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U displacement fields of the corner solder bump induced by the thermal loading from room temperature to 100°C (ΔT=75°C): (a) just after heating to 100°C; (b) after 60 minutes. The contour interval is 417 nm per fringe.
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Macro and micro effects on the shear strain at four corners of the rightmost solder joint (adapted from 4).
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Superposition of macro and micro effects: (a) U displacement field of two solder bumps located at corner of the CSP assembly; (b) failure after an accelerated thermal cycling test (adapted from 2); (c) the distribution of shear strain ε12 in the rightmost solder bump

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