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TECHNICAL PAPERS

Stress and Reliability Analysis of Electronic Packages With Ultra-Thin Chips

[+] Author and Article Information
Sergey Shkarayev

Department of Aerospace and Mechanical Engineering, The University of Arizona, Tucson, AZ 85721e-mail: svs@u.arizona.edu

Sergey Savastiouk, Oleg Siniaguine

Tru-Si Technologies, Inc., Sunnyvale, CA 94086

J. Electron. Packag 125(1), 98-103 (Mar 14, 2003) (6 pages) doi:10.1115/1.1535932 History: Received October 01, 2001; Online March 14, 2003
Copyright © 2003 by ASME
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References

Figures

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Wafer of thickness 50 μm (courtesy of Tru-Si Technologies, Inc.)
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Geometric description of the package
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Characteristic lines and points
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Geometry for the junction of dissimilar materials
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Stress distribution in chip
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Stress distribution in solder bump for baseline design cases 1 and 2—(a) design case 1, thick chip; (b) design case 2, thin chip
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Stress intensity factors, Kθθ, versus chip thickness, u, at various substrate thicknesses, b—(a) corner C, (b) corner B
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Stress intensity factors, K, versus chip thickness, u, at various substrate thicknesses, b—(a) corner A, (b) corner B
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Variation of stresses along the middle plane of a solder bump in the package with underfill—(a) design case 7, (b) design case 8

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