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PAPERS ON RELIABILITY

Parametric Design and Reliability Analysis of Wire Interconnect Technology Wafer Level Packaging

[+] Author and Article Information
Y. T. Lin, C. T. Peng, K. N. Chiang

Dept. of Power Mechanical Engineering, National Tsing Hua University, HsinChu 30013, Taiwan

J. Electron. Packag 124(3), 234-239 (Jul 26, 2002) (6 pages) doi:10.1115/1.1481368 History: Received April 03, 2001; Online July 26, 2002
Copyright © 2002 by ASME
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References

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Daveaux, R., and Benerji, K., 1991, “Fatigue Analysis of Flip Chip Assemblies Using Thermal Stress Simulations and a Coffin-Manson Relation,” 10569-5503/91/0000-0797 IEEE, pp. 797–805.
Goodman, T., and Elenius, P., 1997, “Flex-On-Cap Solder Paste Bumping,” Electronic Components and Technology Conference ’97, pp. 248–253.
Collins, J. A., 1984, “Failure of Materials in Mechanical Design—Analysis, Prediction, Prevention,” pp. 384–387.
Love et al. 1998, “Wire Interconnect Structure for Connecting an Integrated Circuit to a Substrate,” US patent No. 5,773,889, Jun. 30.
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Chiang,  K. N., and Cheng,  H. C., 2000, “On Enhancing Eutectic Solder Joint Using A 2nd-Reflow-Process Approach,” IEEE Transaction on Advanced Packaging, 23(1), pp. 9–14, Feb..
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Yeh,  C. P., Zhou,  Wen X., and Wyatt,  K., 1996, “Parametric Finite Element Analysis of Flip Chip Reliability,” The International journal of Microcircuits and Electronic Packaging, 19(2), pp. 120–127, Second Quarter.
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Cheng,  H. C., Chiang,  K. N., and Lee,  M. H., 1998, “An Alternative Local/Global Finite Element Approach for Ball Grid Array Typed Packages,” ASME Journal of Electronic Packaging, 120, pp. 129–134.
Subbarayan,  G., Ferri,  M. G., and DeFpster,  S. M., 1996, “Reliability of Metallized Ceramic Packages,” IEEE Transactions on Components, Packaging and Manufacturing Technology-Part B, 19, No. 3, pp. 685–691.

Figures

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Flip chip without underfill Laser Moiré phase diagram and refined fringe
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Half FEM Model of WIT wafer level package with 4, 5 and 7 column posts
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Half FEM model of conventional wafer level package with 4 solder bumps
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Illustrations of FEM models of parametric study
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Stress/strain curve of polyimide
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Accumulated equivalent plastic strain versus cycling time of conventional WLP
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Accumulated equivalent plastic strain versus cycling time of WIT Model 1
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Max. strain of outmost column post of WIT Model 2
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One-half finite element model of flip-chip BGA package
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Stress/strain curve of 60Sn/40Pb eutectic solder
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Top and cross-section view of conventional flip-chip BGA package without underfill layer
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Wire interconnect technology (source: Fujitsu)

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