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TECHNICAL BRIEF

Impact of Low Temperatures on Solder Joint Failures

[+] Author and Article Information
Boris Mirman

Suffolk University, Boston, MA 02420-2211

J. Electron. Packag 124(2), 135-137 (May 02, 2002) (3 pages) doi:10.1115/1.1465431 History: Received December 29, 2000; Revised May 31, 2001; Online May 02, 2002
Copyright © 2002 by ASME
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References

Figures

Grahic Jump Location
Four-circuit panel with 16 TSOP-I and 16 TSOP-II
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Daisy-chains of the tested circuit
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Force directions for cooling and heating for “chip on lead” configuration
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Sketch for internal structure of TSOP. (a) “Chip on lead”; (b) “lead on chip”

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