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TECHNICAL PAPERS

In-Plane Packaging Stress Measurements Through Piezoresistive Sensors

[+] Author and Article Information
Ben-Je Lwo

Department of Mechanical Engineering, Chung-Cheng Institute of Technology, National Defense University, Ta-Shi, Tao-Yuan, 335, Taiwan, R.O.C

Tung-Sheng Chen, Yu-Lin Lin

Electrical Engineering, Chung-Cheng Institute of Technology, National Defense University, Ta-Shi, Tao-Yuan, 335, Taiwan, R.O.C

Ching-Hsing Kao

Applied Physics, Chung-Cheng Institute of Technology, National Defense University, Ta-Shi, Tao-Yuan, 335, Taiwan, R.O.C

J. Electron. Packag 124(2), 115-121 (May 02, 2002) (7 pages) doi:10.1115/1.1452244 History: Online May 02, 2002
Copyright © 2002 by ASME
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References

Miura, H., Ikeda S., and Suzuki, N., 1996, “Effect of Mechanical Stress on Reliability of Gate Oxide Film in MOS Transistor,” Proc. Of the 1996 IEEE International Electron Devices Meeting, pp. 743–746.
Van Kessel,  C. G. M., Gee,  S. A., and Murphy,  J. J., 1983, “Quality of Die-attachment and its Relationship to Stress and Vertical Die-Cracking,” IEEE Trans. Compon., Hybrids, Manuf. Technol., CHMT-6, pp. 414–420.
Bastawros,  A. F., and Vososhin,  A. S., 1990, “Thermal Strain Measurements in Electronic Packaging Through Fractional Fringe Moire Interferometry,” ASME J. Electron. Packag., 112, No. 4, pp. 303–308.
Jin,  G., Bao,  N. K., and Chung,  P. S., 1996, “Application of Nondestructive Testing Methods to Electronic Industry Using Computer-Aided Optical Metrology,” Opt. Lasers Eng., 25, No. 2-3, pp. 81–91.
Lau, J. H., 1993, Thermal Stress and Strain in Microelectronics Packaging, Van Nostrand Reinhold Co., New York.
Beaty,  R. E., Suhling,  J. C., Moody,  C. A., Bittle,  D. A., Johnson,  R. W., Butler,  R. D., and Jaeger,  R. C., 1992, “Piezoresistive Coefficient Variation in Silicon Stress Sensors Using a Four-Point Bend Text Fixture,” IEEE Trans. Compon., Hybrids, Manuf. Technol., CHMT-15, pp. 904–913.
Zou,  Y., Suhling,  J. C., Johnson,  R. W., Jaeger,  R. C., and Mian,  A. K. N., 1999, “In-Situ Stress State Measurements During Chip-on-Board Assembly,” IEEE Tran. on Electronic Packaging Manufacturing, 22, No 1, pp. 35–52.
Lin, C. Y. et al., 1999, “Calibration of Piezoresistive Stress Sensors in Electronic Packaging,” The 6th Symposium on Nano Device Tech., pp. 173–176.
Chen, T. S. et al., 2000, “Application of Microelectronic Devices for Package-Induced Stress Measurement,” Proc. of the 5th Annual Pan-Pacific Microelectronic Symposium, pp. 302–306.
Lwo,  B. J., Kao,  C. H., Chen,  T. S., and Chen,  Y. S., 2002, “On the study of piezoresistive Stress Sensors for Microelectronic Packaging,” ASME J. Electron. Packag., 124, No. 1, pp. 22–26.
Jaeger,  R. C., Suhling,  J. C., Carey,  M. T., and Johnson,  R. W., 1993, “Off-Axis Sensor Rosette for Measurement of the Piezoresistive Coefficients of Silicon,” IEEE Trans. Compon., Hybrids, Manuf. Technol., 16, No. 8, pp. 925–930.
Lwo,  B. J., Chen,  Y. S., Chen,  T. S., Lee,  G. M., Kao,  C. H., Lin,  C. Y., and Tseng,  K. F., 2000, “Temperature Calibration on Piezoresistive Sensors,” J. of Chung-Cheng Institute of Technology, 29, No. 1, pp. 15–22. (In Chinese)

Figures

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The configuration of a four-resistor rosette
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Rotation of coordinate systems
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Idealized representation (a) and actual schematic of the 4PB structure (b)
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Relative resistance changes for n-type resistors (a) and p-type resistors (b) for calibration
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σ11 versus temperature for batch #1(a), batch #2(b), and batch #3(c) of test sample
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σ22 versus temperature for batch #1(a), batch #2(b), and batch #3(c) of test sample
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σ12 versus temperature for batch #1 of test sample
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σ11 versus power for batch #1(a) and batch #3(b) of test sample
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σ22 versus power for batch #1(a) and batch #3(b) of test sample
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σ12 versus power for batch #1 of test sample

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