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TECHNICAL PAPERS

Creep Analysis of Wafer Level Chip Scale Package (WLCSP) With 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints and Microvia Build-Up Printed Circuit Board

[+] Author and Article Information
John H. Lau, Stephen H. Pan, Chris Chang

Agilent Technologies, Inc., 5301 Stevens Creek Blvd., Santa Clara, CA 95052

J. Electron. Packag 124(2), 69-76 (May 02, 2002) (8 pages) doi:10.1115/1.1400995 History: Received August 08, 2000; Online May 02, 2002
Copyright © 2002 by ASME
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References

Figures

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Schematic of a chip with pad redistribution
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Schematic of one-half of the WLCSP assembly
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Dimensions of the solder joint
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Finite element model of one-half of the WLCSP assembly
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Creep constitutive relations of the lead-free solders
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Thermal cycling condition
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Deformed shapes at 588 sec (a), 4188 sec (b), 7788 sec (c), 11388 sec (d), and 14988 sec (e)
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Effective creep strain contours in the corner solder joint at 588 sec (a), 4188 sec (b), 7788 sec (c), 11388 sec (d), and 14988 sec (e)
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Effective stress contours in the corner solder joint at 588 sec (a), 4188 sec (b), 7788 sec (c), 11388 sec (d), and 14988 sec (e)
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Shear stress and shear creep strain hysteresis loops for 62Sn2Ag36Pb corner solder joint
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Shear stress and shear creep strain hysteresis loops for 96.5Sn3.5Ag corner solder joint
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Shear stress and shear creep strain hysteresis loops for 100In corner solder joint
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Shear stress time-history for 62Sn2Ag36Pb, 96.5Sn3.5Ag, and 100In corner solder joints
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Shear creep strain time-history for 62Sn2Ag36Pb, 96.5Sn3.5Ag, and 100In corner solder joints
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Schematic of WLCSP on PCB with microvia build-up circuits
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Deformed shapes at 588 sec (a), 4188 sec (b), 7788 sec (c), 11388 sec (d), and 14988 sec (e), (build-up PCB)
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Shear stress and shear creep strain hysteresis loops for 62Sn2Ag36Pb corner solder joint on build-up PCB
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Shear stress time-history for 62Sn2Ag36Pb corner solder joint on build-up PCB
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Shear creep strain time-history for 62Sn2Ag36Pb corner solder joint on build-up PCB

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