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TECHNICAL PAPERS

On the Study of Piezoresistive Stress Sensors for Microelectronic Packaging

[+] Author and Article Information
Ben-Je Lwo

Department of Mechanical Engineering, Chung-Cheng Institute of Technology, National Defense University, Ta-Shi, Tao-Yuan, 335, Taiwan, R.O.C.e-mail: lwob@ccit.edu.tw

Ching-Hsing Kao

Department of Applied Physics, Chung-Cheng Institute of Technology, National Defense University, Ta-Shi, Tao-Yuan, Taiwan, 335, R.O.C.

Tung-Sheng Chen, Yao-Shing Chen

Department of Electrical Engineering, Chung-Cheng Institute of Technology, National Defense University, Ta-Shi, Tao-Yuan, Taiwan, 335, R.O.C.

J. Electron. Packag 124(1), 22-26 (Feb 21, 2000) (5 pages) doi:10.1115/1.1414134 History: Received February 21, 2000
Copyright © 2002 by ASME
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References

Miura, H., Ikeda S., and Suzuki, N., 1996, “Effect of Mechanical Stress on Reliability of Gate Oxide Film in MOS Transistor,” Proc. Of the 1996 IEEE International Electron Devices Meeting, pp. 743–746.
Miura, H., and Ikeda S., 1998, “New Mechanical Reliability Issues for Deep-submicron Devices,” Proc. Of the Semiconductor Manufacturing Technology Workshop, pp. 140.
Van Kessel,  C. G. M., Gee,  S. A., and Murphy,  J. J., 1983, “Quality of Die-attachment and its Relationship to Stress and Vertical Die-Cracking,” IEEE Trans. Compon., Hybrids, Manuf. Technol., CHMT-6, pp. 414–420.
Seraphim, D. P., Lasky, R. C., and Li, C-Y, 1993, Principle of Electronic Packaging, McGraw-Hill, New York.
Bastawros,  A. F., and Vososhin,  A. S., 1990, “Thermal Strain Measurements in Electronic Packaging Through Fractional Fringe Moire Interferometry,” ASME J. Electron. Packag., 112, No. 4, pp. 303–308.
Jin,  G., Bao,  N. K., and Chung,  P. S., 1996, “Application of Nondestructive Testing Methods to Electronic Industry Using Computer-Aided Optical Metrology,” Opt. Lasers Eng., 25, No. 2–3, pp. 81–91.
Lau, J. H., 1993, Thermal Stress and Strain in Microelectronics Packaging, Van Nostrand Reinhold Co., New York.
Bastawros, A. F., and Vososhin, A. S., 1990, “In-Situ Calibration of Stress Chips,” Proc. of 40th Electronic Component and Technology Conference, IEEE, pp. 791–795.
Beaty, R. E., Suhling, J. C., Moody, C. A., Bittle, D. A., Johnson, R. W., Butler, R. D., and Jaeger, R. C., 1990, “Calibration Considerations for Piezoresistive-based Stress Sensors,” Proc. 40th Electronic Component and Technology Conference, IEEE, pp. 797–806.
Beaty,  R. E., Suhling,  J. C., Moody,  C. A., Bittle,  D. A., Johnson,  R. W., Butler,  R. D., and Jaeger,  R. C., 1992, “Piezoresistive Coefficient Variation in Silicon Stress Sensors Using a Four-Point Bend Text Fixture,” IEEE Trans. Compon., Hybrids, Manuf. Technol., CHMT-15, pp. 904–913.
Lwo,  B. J., Chen,  Y. S., Chen,  T. S., Lee,  G. M., Kao,  C. H., Lin,  C. Y., and Tseng,  K. F., 2000, “Temperature Calibration on Piezoresistive Sensors,” J. of Chung-Cheng Institute of Technology, 29, No. 1, pp. 15–22 (In Chinese).
Kirkup, L., 1994, Experimental Methods—An Introduction to the Analysis and Representation of Data, Wiley, Brisbane.
Lin, C. Y., Chen, T. S., Lwo, B. J., Chen, Y. S., Ho, T. T., Lee C. Y., and Kao, C. H., 1999, “Calibration of Piezoresistive Stress Sensors in Electronic Packaging,” Proceeding of the Sixth Symposium on Nano Device Technology, pp. 173–176.
Sweet,  J. N., and Peterson,  D. W., 1993, “High Accuracy Die Mechanical Stress Measurement with ATC04 Assembly Test Chip,” 1993 IRW Final Report, pp. 90–97.
Tufte,  O. N., and Stelzer,  E. L., 1963, “Piezoresisitve Properties of Silicon Diffused Layers,” J. Appl. Phys., 34, pp. 313, and 1964 “Piezoresisitve Properties of Heavily Doped n-type Silicon,” Phys. Rev., 133A, pp. 1705.
Natarajan, B., and Bhattacharyya, B., 1986, “Die Surface Stresses in a Molded Plastic Package,” Proc. 36th Electronic Components Conference, IEEE, pp. 544–551.

Figures

Grahic Jump Location
Configuration of a typical four-resistor rosette
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A typical MQFP structure
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Ideal representation (left) and actual 4PB fixture (right)
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σx due to process effect, measured by n-type sensors
Grahic Jump Location
σy due to process effect, measured by n-type sensors
Grahic Jump Location
σx due to process effect, measured by a typical p-type sensor
Grahic Jump Location
Stress differences due to process effect, measured by p-type sensors
Grahic Jump Location
σx due to power generated in a chip, measured by n-type sensors
Grahic Jump Location
σy due to power generated in a chip, measured by n-type sensors

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