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PAPERS ON RELIABILITY

A Nested Finite Element Methodology (NFEM) for Stress Analysis of Electronic Products—Part II: Durability Analysis of Flip Chip and Chip Scale Interconnects

[+] Author and Article Information
Krishna Darbha, Abhijit Dasgupta

CALCE Electronic Products and Systems Center, University of Maryland, College Park, MD 20742

J. Electron. Packag 123(2), 147-155 (Oct 10, 2000) (9 pages) doi:10.1115/1.1328745 History: Received October 10, 2000
Copyright © 2001 by ASME
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References

IPC SM 785, 1992, “guidelines for accelerated testing of surface mount solder attachments,” Proposed Standard of IPC Surface Mount Task Group, Institute for Interconnecting Packing Electronic Circuits, Lincolnwood, IL.
Engelmaier, W., 1982, “Fatigue life of leadless chip carrier solder joints during power cycling,” Proceedings of the Technical Program of the 2nd Annual International Electronics Packaging Society Conference, San Diego, CA, Nov. 15–17, 1982.
Yeh,  C., Zhou,  W., and Wyatt,  K., 1996, “Parametric finite element analysis of flip chip reliability,” Microcircuits and Electronic Packaging,19, No. 2, pp. 120–127.
Lau, J. H., and Pao, Y, 1997, Solder joint reliability of BGA, CSP and fine pitch SMT assemblies, McGraw-Hill, NY.
Doi,  K., Hirano,  N., Okada,  T., Hiruta,  Y., Sudo,  T., and Mukai,  M., 1996, “Prediction of thermal fatigue for encapsulated flip chip interconnection,” Microcircuits and Electronic Packaging,19, No. 3, pp. 231–237.
Schubert, A., Dudek, R., Auersperg, J., Vogel, D., Michel, B., and Reichl, H., 1997, “Thermo-Mechanical reliability analysis of flip chip assemblies by combined microDAC and the finite element method” INTERpack ’97, EEP-Vol. 19-1, pp. 1647–1654.
Le Gall, C. A., Qu, J., and McDowell, D. L., 1997, “Influence of die size on the magnitude of thermomechanical stresses in flip chips directly attached to printed wiring board,” InterPACK’97, EEP-Vol. 19-2, pp. 1663–1670.
Okura, J. H., Darbha, K., Shetty, S., Dasgupta, A., and Caers, J., 1999, “Underfill design guidelines for flip chip on board assemblies,” ECTC Conference, San Diego, CA.
Dasgupta, A., Oyan, C., Booker, D., and Pecht, M., 1992, “Solder Creep-Fatigue Analysis by an Energy-Partitioning Approach,” Trans. ASME JEP, Vol. 114, pp. 152–160.
Darbha, K., and Dasgupta, A., 1999, “A Nested Finite Element Methodology for stress analysis of flip chip on board Assemblies-Part 1: Elastic Analysis,” ASME Interpack ’99, June, Maui, Hawaii.
Okura, J. H., Darbha, K., and Dasgupta, A., 1998, “Effect of underfill in flip chip on board assemblies,” 10th Symposium on Surface Mount Assemblies, ASME Winter Annual Conference, Anaheim, CA.
Darbha,  K., Okura,  J. H., Shetty,  S., Dasgupta,  A., Reinikainen,  T., Zhu,  J., and Caers,  J., 1999, “Thermomechanical Durability Analysis of Flip Chip Solder Interconnects: Part 2-with underfill,” ASME J. Electron. Packag., 121, No. 4, pp. 237–241.
Baggerman,  A. F. J., Caers,  J. F. J. M., Wondergem,  J. J., and Wagemans,  A. G., 1996, “Low-cost flip chip on board,” IEEE Transactions on Components, Packgaing, and Manufacturing Technology-Part B, 19, No. 4, pp. 736–746.
Lau, J., and Ricky-Lee, S. W., 1999, Chip Scale Package-Design, materials, processes, reliability and application McGraw Hill, NY, Chapter 16, pp. 259–282.
Banks D. R., Heim, C. G., and Lewis, R. H., 1993, “Second-Level assembly of column-grid array packages,” Proceedings of the SMI Conference, Aug. 1993, pp. 92–98.
Pecht, M., 1991, Handbook of electronic packaging and design, Marcel Dekker, NY, pp. 732–734.
Tribula, D., and Morris, J. W., 1989, “Creep shear of experimental solder joints,” ASME Winter Annual Meeting, 89-WA/EEP-30, San Francisco, CA.

Figures

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Schematic illustration of nesting localized subelements
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NFEM contour plot of von Mises stress
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CFEM contour plot of von Mises stress
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Parametric study of underfill properties (CTE is in per °C)
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Cyclic thermal loading profile
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Comparison of average creep work dissipated recorded at top left corner of solder interconnect
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Comparison of shear stress-shear strain hysteresis for FCOB assembly with underfill
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Comparison of von Mises stress contour plot for CSP-BGA assembly: nominal versus skinny versus column solder geometry
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Elastic analysis of CSP-BGA assembly with and without a void in the solder interconnect using CFEM model
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Elastic analysis of CSP-BGA assembly with and without a void in the solder interconnect using NFEM model
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Comparison of von Mises stress contours for CSP-BGA assembly subjected to unit temperature change
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Illustration of CFEM mesh with “zoom-in” of the solder interconnect of CSP-BGA assembly
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Schematic illustration of NFEM mesh with subelements to capture stress concentration site (not to scale)
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Schematic illustration of CSP-BGA assembly
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NFEM-2 mesh of solder in FCOB. Copper bond-pad modeled as a main element (228 degrees of freedom)
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NFEM-1 mesh of FCOB. Copper bond-pad is modeled as a subelement (186 degrees of freedom)
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CFEM mesh for flip chip with underfill (5050 degrees of freedom)
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Schematic illustration of FCOB with underfill

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