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PAPERS ON RELIABILITY

A Nested Finite Element Methodology (NFEM) for Stress Analysis of Electronic Products—Part II: Durability Analysis of Flip Chip and Chip Scale Interconnects

[+] Author and Article Information
Krishna Darbha, Abhijit Dasgupta

CALCE Electronic Products and Systems Center, University of Maryland, College Park, MD 20742

J. Electron. Packag 123(2), 147-155 (Oct 10, 2000) (9 pages) doi:10.1115/1.1328745 History: Received October 10, 2000
Copyright © 2001 by ASME
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References

Figures

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Schematic illustration of nesting localized subelements
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Comparison of von Mises stress contour plot for CSP-BGA assembly: nominal versus skinny versus column solder geometry
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Elastic analysis of CSP-BGA assembly with and without a void in the solder interconnect using CFEM model
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Elastic analysis of CSP-BGA assembly with and without a void in the solder interconnect using NFEM model
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Comparison of von Mises stress contours for CSP-BGA assembly subjected to unit temperature change
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Illustration of CFEM mesh with “zoom-in” of the solder interconnect of CSP-BGA assembly
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Schematic illustration of NFEM mesh with subelements to capture stress concentration site (not to scale)
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Schematic illustration of CSP-BGA assembly
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Comparison of shear stress-shear strain hysteresis for FCOB assembly with underfill
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Comparison of average creep work dissipated recorded at top left corner of solder interconnect
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Cyclic thermal loading profile
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Parametric study of underfill properties (CTE is in per °C)
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CFEM contour plot of von Mises stress
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NFEM contour plot of von Mises stress
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NFEM-2 mesh of solder in FCOB. Copper bond-pad modeled as a main element (228 degrees of freedom)
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NFEM-1 mesh of FCOB. Copper bond-pad is modeled as a subelement (186 degrees of freedom)
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CFEM mesh for flip chip with underfill (5050 degrees of freedom)
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Schematic illustration of FCOB with underfill

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