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TECHNICAL PAPERS

Applications of a Decomposed Analysis Procedure for Area-Array Packages

[+] Author and Article Information
Terrace B. Thompson, Ganesh Subbarayan

Department of Mechanical Engineering, University of Colorado at Boulder, Boulder, CO 80309

J. Electron. Packag 123(2), 132-140 (Sep 14, 2000) (9 pages) doi:10.1115/1.1339197 History: Received August 30, 1999; Revised September 14, 2000
Copyright © 2001 by ASME
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References

Figures

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A heuristic decomposition of area-array packages
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Parametric representation of displacement fields at solder/PCB and solder/component interfaces
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Relative displacements between the bottom and top interfaces of a solder joint
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A typical finite element model of the solder joint
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Typical code input deck for decomposed analysis
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Flow control in the program
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Finite element models of hypothetical 2-D electronic packages
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The 3-D finite element model of the 5×5 package used for verification of decomposed analysis results
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The cross-section of the hypothetical 5×5 package
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The 3-D finite element model of the 225 I/O PBGA electronic package
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Cross-section of the 225 I/O PBGA electronic package
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A comparison of displacements at solder joints J1-J6 between decomposed solution and full 3-D finite element analysis
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A comparison of displacements at diagonal solder joints 1-8 (J1-J8) between decomposed solution and full 3-D finite element analysis
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Relative shear displacement comparisons (Zhang et al. 8)
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225 I/O PBGA shear gradient/relative error plot

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