Flip-Chip BGA Design to Avert Die Cracking

[+] Author and Article Information
J.-B. Han

Agilent Technologies, Imaging Electronics Division, Hardcopy Electronics Operation, 2 Corporation Road, Corporation Place 05-01, Singapore 618494, Singapore e-mail: jiang-bo_han@agilent.com

J. Electron. Packag 123(1), 58-63 (Oct 29, 1999) (6 pages) doi:10.1115/1.1329130 History: Received October 29, 1999
Copyright © 2001 by ASME
Your Session has timed out. Please sign back in to continue.


Mathieu,  B., and Dasgupta,  A., 1994, “A Fractional-Factorial Numerical Technique for Stress Analysis of Glass-to-Metal Lead Seals,” ASME J. Electron. Packag., 116, pp. 98–104.
Jih,  E., and Pao,  Y.-H., 1995, “Evaluation of Design Parameters for Leadless Chip Resistors Solder Joints,” ASME J. Electron. Packag., 117, pp. 94–117.
Mertol,  A., 1995, “Application of the Taguchi Method on the Robust Design of Molded 225 Plastic Ball Grid Array Packages,” IEEE Trans. Compon., Packag. Manuf. Technol., Part B, 18, pp. 734–743.
Mertol,  A., 1997, “Optimization of High Pin Count Cavity-up Enhanced Plastic Ball Grid Array (EPBGA) Packages for Robust Design,” IEEE Trans. Compon., Packag. Manuf. Technol., Part B, 20, pp. 376–388.
Yeh,  C.-P., Zhou,  W. X., and Wyatt,  K., 1996, “Parametric Finite Element Analysis of Flip Chip Reliability,” Int. J. Microcircuits Electron. Packag., 19, pp. 120–127.
Villani,  A., and Hsu,  S. C., 1996, “Reliablity of Low Cost Copper Heat Spreader Pin Grid Array Ceramic Packages,” Int. J. Microcircuits Electron. Packag., 19, pp. 138–145.
Pecht,  M. G., 1998, “Virtual Product Development,” IEEE Trans. Compon., Packag. Manuf. Technol., Part A, 21, p. 610.
Lindell,  M., Stoaks,  P., Carey,  D., and Sandborn,  P., 1998, “The Role of Physical Implementation in Virtual Prototyping of Electronic Systems,” IEEE Trans. Compon., Packag. Manuf. Technol., Part A, 21, pp. 611–616.
Evans, T. C., 1999, “Future Packaging Reliability Test,” HDP/MCM-1999 Proceedings, Denver, Colorado, pp. 389–394.
Chin,  S.-W., Rajan,  S. D., Nagaraj,  B. K., and Mahalingam,  M., 1994, “Automated Design Tool for Examining Microelectronic Packaging Design Alternatives,” IEEE Trans. Compon., Packag. Manuf. Technol., Part B, 17, pp. 76–82.
Broek, D., 1982, Elementary Engineering Fracture Mechanics, Martinus Nijhoff, Boston.
Van Vroonhoven,  J. C. W., 1993, “Effects of Adhesion and Delamination on Stress Singularities in Plastic-Packaged Integrated Circuits,” ASME J. Electron. Packag., 115, pp. 28–33.
Hu,  K. X., Yeh,  C. P., Wu,  X. S., and Wyatt,  K., 1996, “An Interfacial Delamination Analysis for Multichip Module Thin Film Interconnects,” ASME J. Electron. Packag., 118, pp, 206–213.
Sato,  M., Yoshioka,  S., Inoue,  A., Tani,  S., and Iwaoka,  M., 1997, “Analysis of Delamination Arrest Effect of Dimples on Interface in LSI Package,” JSME Int. J., Ser. A, 40, pp. 58–64.
Fan, X. J., Teo, Y. C., Teo, P. S., and Lim, T. B., 1998, “Die Cracking Analysis in Flip Chip PBGA,” Proceedings of the Third International Symposium on Electronic Packaging Technology, Beijing, China, pp. 458–463.
Liu,  X. K., Suo,  Z., and Ma,  Q., 1999, “Split Singularities: Stress Field Near the Edge of a Silicon Die on a Polymer Substrate,” Acta Mater., 47, pp. 67–76.
Liu,  X. K., Suo,  Z., Ma,  Q., and Fujimoto,  H., 2000, “Developing Design Rules to Avert Cracking and Debonding in Integrated Circuit Structures,” Eng. Fract. Mech., 66, pp. 387–402.
Wang,  J., Qian,  Z., and Liu,  S., 1998, “Process Induced Stresses of a Flip-Chip Packaging by Sequential Processing Modeling Technique,” ASME J. Electron. Packag., 120, pp. 309–313.
Owen, D. R. J., and Fawkes, A. J., 1983, Engineering Fracture Mechanics: Numerical Methods and Applications, Pineridge Press, Swansea, UK.
Lee, T. W., and Pabbisetty, S. V., eds., 1993, Microelectornic Failure Analysis: Desk Reference, 3rd Ed., ASM International (The Material Information Society), Materials Part, OH, p. 366.


Grahic Jump Location
Cross-sectional view (two-dimensional model) of flip-chip BGA package
Grahic Jump Location
Two basic models used: (a) model I—whole package with a crack on backside of die, and (b) model II—half a package with a crack on backside of die
Grahic Jump Location
Finite element mesh for the basic model II
Grahic Jump Location
Relation between strain energy release rate and crack location (x=0 located at die center)
Grahic Jump Location
Relation between SIF (KI) and crack length
Grahic Jump Location
Basic concept of virtual DOE
Grahic Jump Location
Bar chart of main effect of design parameters
Grahic Jump Location
Effects of (a) substrate thickness, (b) die thickness, (c) underfill modulus, and (d) bump height on die cracking
Grahic Jump Location
Contour plot of the interaction between substrate thickness and die thickness




Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In