Flip-Chip BGA Design to Avert Die Cracking

[+] Author and Article Information
J.-B. Han

Agilent Technologies, Imaging Electronics Division, Hardcopy Electronics Operation, 2 Corporation Road, Corporation Place 05-01, Singapore 618494, Singapore e-mail: jiang-bo_han@agilent.com

J. Electron. Packag 123(1), 58-63 (Oct 29, 1999) (6 pages) doi:10.1115/1.1329130 History: Received October 29, 1999
Copyright © 2001 by ASME
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Cross-sectional view (two-dimensional model) of flip-chip BGA package
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Two basic models used: (a) model I—whole package with a crack on backside of die, and (b) model II—half a package with a crack on backside of die
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Finite element mesh for the basic model II
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Relation between strain energy release rate and crack location (x=0 located at die center)
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Relation between SIF (KI) and crack length
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Basic concept of virtual DOE
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Bar chart of main effect of design parameters
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Effects of (a) substrate thickness, (b) die thickness, (c) underfill modulus, and (d) bump height on die cracking
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Contour plot of the interaction between substrate thickness and die thickness




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