0
TECHNICAL PAPERS

Evaluation of Smear and Its Effect on the Mechanical Integrity of Plated Through Hole-Inner Plane Interface in Thick Printed Wiring Boards

[+] Author and Article Information
R. Venkatraman

LSI Logic Corporation, 3140 Alfred Street, Santa Clara, CA 95054

K. Ramakrishna

Digital DNA Laboratories, Semiconductor Products Sector, Motorola, Inc., Austin, TX 78712

K. Knadle, W. T. Chen, G. C. Haddon

Microelectronics Division, IBM Corporation, Endicott, NY 13760-8000

J. Electron. Packag 123(1), 6-15 (Jul 01, 2000) (10 pages) doi:10.1115/1.1326437 History: Received July 01, 2000
Copyright © 2001 by ASME
Your Session has timed out. Please sign back in to continue.

References

Markovich, V. R., and Poch, F. S., 1989, “Plated Through Hole Technology,” Principles of Electronic Packaging, Seraphim, D. P., Lasky, R., and Li, C-Y., eds., McGraw-Hill, New York, NY, pp. 519–538.
Oien, M. A., 1976, “A Simple Model for the Thermomechanical Deformation of Plated-Through-Holes in Multilayer Printed Wiring Boards,” Proc. of the 14th Annual Reliability Physics Symp., Sponsored by IEEE Electron Device Soc., and IEEE Reliability Group, held in Las Vegas, NV, Apr. 20–22, pp. 121–128.
Oien, M. A., 1976, “Methods for Evaluating Plated-Through-Hole Reliability,” Proc. of the 14th Annual Reliability Physics Symp., Sponsored by IEEE Electron Device Soc., and IEEE Reliability Group, held in Las Vegas, NV, Apr. 20–22, pp. 129–131.
Barker,  D., Pecht,  M., Dasgupta,  A., and Naqvi,  S., 1991, “Transient Thermal Stress Analysis of a Plated Through Hole Subjected to Wave Soldering,” ASME J. Electron. Packag., 113, No. 2, pp. 149–155.
Barker, D., and Dasgupta, A., 1993, “Thermal Stress Issues in Plated-Through-Hole Reliability,” Thermal Stress and Strain in Microelectronics Packaging, Lau, J. H., ed., van Nostrand Reinhold, New York, NY, pp. 648–683.
Vecchio,  K. S., and Hertzberg,  R. W., 1988, “Analysis of Long Term Reliability of Plated Through Holes in Multilayer Interconnection Boards Part A: Stress Analysis and Material Characterization,” Microelectron. Reliab., 26, No. 4, pp. 715–732.
Kurosawa, K., Takeda, Y., Takaji, K., and Kawamata, H., 1981, “An Investigation of Reliability Behavior of Plated Through Holes in Multilayer Printed Wiring Boards,” IPC Technical Paper, IPC-TP-385, Inst. for Interconnecting and Packaging Electronic Circuits, Lincolnwood, IL, pp. 1–13.
Mirman,  B. A., 1988, “Mathematical Model of Plated Through Hole Under a Load Induced by Thermal Mismatch,” IEEE Trans. Compon., Hybrids, Manuf. Technol., 11, No. 4, pp. 506–511.
Ozmat, B., Walker, H. and Elkins, M., 1990, “A nonlinear thermal strain analysis of the plated through holes of printed wiring boards,” Proc. of the Technical Conf., Intl. Electronic Packaging Conf., Marlborough, MA, Sep. 10–12, pp. 359–381.
Bhandarkar,  S. M., Dasgupta,  A., Barker,  D., Pecht,  M., and Engelmaier,  W., 1991, “Influence of Selected Design Variables on Thermo-Mechanical Stress Distribution in Plated-Through-Hole Structures,” ASME J. Electron. Packag., 114, No. 1, pp. 8–13.
Iannuzelli, R. J., 1991, “Predicting Plated Through Hole Reliability in High Temperature Manufacturing Processes,” Proc. of the 41st Electronic Components & Technology Conf., Atlanta, GA, IEEE CHMT Society, pp. 410–421.
Ramakrishna, K., Subbarayan, G., and Sammakia, B. G., 1992, “Effect of Non-Uniformities and Defects on PTH Strain during Assembly and Accelerated Thermal Cycling,” Proc. of the First ASME/JSME Joint Electronic Packaging Conf., Chen, W. T., and Abe, H., eds., EEP-Vol. 1, Published by Electronic Packaging Division, ASME, New York, NY, organized by ASME/JSME, Milpitas, CA, April 9–12, pp. 891–909.
Ramakrishna, K., Chen, W. T., Thiel, G. H., Steinwall, J. E., and Niu, T. M., 1994, “Plated Through Holes in Thick Printed Wiring Boards: Interaction Between Design, Materials and Assembly Processes,” Mechanics and Materials for Electronic Packaging: Vol. 1: Design and Process Issues in Electronic Packaging, Chen, W. T., Nguyen, L. T., and Winterbottom, W. L., eds., AMD-Vol. 195, pp. 1–10, 1994 ASME International Mechanical Engineering Congress and Conference, held in Chicago, IL, Nov. 6–11, 1994.
Ramakrishna, K., Thiel, G. H., and Sammakia, B. G., 1997 “Analysis of Thermo-mechanical Stresses and Strains Induced in the Plated Through Holes in Thick Advanced Printed Wiring Boards,” Advances in Electronic Packaging 1997, E. Suhir, M. Shiratori, Y. C. Lee, and G. Subbarayan, eds., Proc. of the INTERpack ’97, an International Electronic Packaging Conf. held in Mauna Lani, Hawaii, June 15–19, EEP-Vol. 19-2, pp. 1639–1646.
Subbarayan,  G., Ramakrishna,  K., and Sammakia,  B. G., 1997, “The Impact of Interfacial Adhesion on PTH and Via Reliability,” ASME J. Electron. Packag., 119, No. 4, pp. 260–267.
Ammann, H. H., and Jocher, R. W., 1976, “Measurement of Thermo-Mechanical Strain in Plated Through Holes,” Proc. of the 14th Annual Reliability Physics Symp., Sponsored by the IEEE Electron Devices Society, and IEEE Reliability Group, held in Las Vegas, NV, Apr. 20–22, pp. 118–120.
Tossell,  D. A., and Ashbee,  K. H. G., 1989, “High Resolution Optical Interference Investigation of Deformation Due to Thermal Expansion Mismatch Around Plated Through Holes In Multilayer Circuit Boards,” J. Electron. Mater., 18, No. 2, pp. 275–286.
Ashbee,  K. H. G., and Tossell,  D. A., 1989, “Internal Stresses Adjacent to a Hole Through a Multilayer Wiring Board,” J. Adhes., 29, Nos. 1–4, pp. 131–140.
Gross, T. S., Watt, D. W., and Hening, S. D., 1990, “Thermally Induced Displacement Field Around Plated Through Holes on a Constrained Coefficient of Expansion Printed Wiring Board Measured by Holographic Interferometry,” Proc. of the Technical Conf., Intl. Electronic Packaging Conf., Marlborough, MA, Sept. 10–12, pp. 165–178.
Gross,  T. S., Perault,  J. A., and Watt,  D. W., 1994, “An Experimental Investigation of Deformation of Plated Holes for a Single 30-210-30°C Thermal Cycle,” ASME J. Electron. Packag., 116, No. 3, pp. 1–5.
Lee,  L. C., Darekar,  V. S., and Lim,  C. K., 1984, “Micromechanisms of Multilayer Printed Circuit Boards,” IBM J. Res. Dev., 28, No. 6, pp. 711–718.
Anon, 1994, Product information published by IBM Microelectronics Division, 1701 North Street, Endicott, NY.
Takagi, K., and Kobayashi, T., 1990, “Reliability Evaluation of Interconnections using Plated Through Hole with Resin Smear in Multilayer Printed Boards,” Technical Paper B2/1, Proc. of Printed Circuit World Convention, UK, June.
Niu, T. M., Burke, E. J., Black, W. E., and Case, J. R., 1992, “6-axis Submicron Fatigue Tester,” Proc. of the First ASME/JSME Joint Electronic Packaging Conf., Chen, W. T., and Abe, H., eds., EEP-Vol. 1, Published by Electronic Packaging Division, ASME, New York, NY, organized by ASME/JSME, Milpitas, CA (April 9–12, 1992), pp. 937–945.
Weiss,  R. E., 1977, “The Effect of Drilling Temperature on Multilayer Board Hole Quality,” Circ. World, 3, pp. 8–14.
Hagge,  J. K., 1977, “Drilling Multilayer Glass-PTFE Circuit Boards,” Circ. World, 3, p. 8.
Tuck, J., 1983, “Small-hole Drilling,” Circuits Manufacturing, Feb.
Murray, J., 1984, “Challenges in Drilling,” Circuits Manufacturing, Oct.
Murray, J., 1984, “On Drilling,” Circuit Manufacturing, Dec.
Berlin, A. J., 1985, “Excessive Drilling Heat Leads to Board Failures,” Electronic Packaging and Production, Jan., p. 168.
Vega-Marchena, Z., 1987, “An Investigation of Multilayer Printed Circuit Board Drill Smear,” Ph.D. dissertation, Dept. of Mech. Eng., Univ. of Texas, Austin, TX.
Kramer,  E. J., Chen,  W. T., and Strope,  D. H., 1990, “Birefringence in Epoxy Glass Laminates Due to Hole Drilling,” IBM Internal Report, Microelectronics Division, IBM Corporation, Endicott, NY.
Anon, 1994, “LATEST: Circuit Reliability Tester,” Product information, IBM Microelectronics Division, 1701 North Street, Endicott, NY.
Anon, 1996, “ANSYS Engineering Analysis System User’s Manual,” Revision 5.3, ANSYS, Inc., Cannonsburg, PA.
Wu,  T. Y., Guo,  Y., and Chen,  W. T., 1993, “Thermal-Mechanical Strain Characterization for Printed Wiring Boards,” IBM J. Res. Dev., 37, No. 5, pp. 621–634.
Carslaw, H. S., and Jaeger, J. C., 1959, Conduction of Heat in Solids, 2nd Ed., Oxford Univ. Press, Oxford, U.K., pp. 188–213.

Figures

Grahic Jump Location
Schematic showing the stitch pattern connecting PTHs in tested samples
Grahic Jump Location
Schematic showing the geometry of resin-filled areas around unconnected copper power planes
Grahic Jump Location
Determination of percentage smear in PTH - inner plane connections
Grahic Jump Location
Variation of shear stress, σrz, along the PTH/dielectric (and IP) interface in the clearance hole region for cases without and with inner plane connections for a ΔT of 102°C
Grahic Jump Location
Variation of shear stress, σrz, along the PTH/IP interface for interior and external IP connections for a ΔT of 102°C
Grahic Jump Location
A peel test in progress
Grahic Jump Location
Schematic of cross section of PTH peel specimen. The distance “x” was not uniform through the length of the sample and was measured accurately for comparison purposes.
Grahic Jump Location
Backscattered SEM image of a copper inner plane: (a) before hole clean and (b) after hole clean. The smear coverage seen in (a) was the worst case of coverage seen.
Grahic Jump Location
A typical plot of peel load versus peel length. The arrows correspond to resin rich areas along the cross-section of the sample. Each of the peaks was found to correspond to a glass bundle attached to the PTH along its length. The overall graph appears to increase with peel length due to the nonuniformity in the sectioning explained in the text.
Grahic Jump Location
Plot showing the effect of desmearing on the adhesion of the PTH barrel copper to the resin rich areas. Clearly, the hole clean operation enhances the adhesion.
Grahic Jump Location
Birefringence patterns from (a) drilled hole with high drill hits and (b) with low drill hits
Grahic Jump Location
Estimated drill temperature as a function of birefringence ring thickness calculated using Eq. (1). The contact time and the position along the cross section of the board corresponded to the location where the B-ring measurement was taken.
Grahic Jump Location
Optical micrographs of coupons failed in ATC testing. The barrel cracks are indicated by arrows. Note that the cracks in the barrel lie at the interface between the resin rich areas and the glass bundles.
Grahic Jump Location
PTH barrel failure locations after ATC. There are 18 PTHs in the sample. The shaded areas indicate the glass bundle areas and the white areas indicate the pure resin areas measured experimentally. Each failure location is indicated by a solid square. Note that most of the failures lie close to the border between the glass bundle and resin rich areas.
Grahic Jump Location
Variation of equivalent plastic strain, εe, along the PTH without and with inner plane connections for a ΔT of 102°C
Grahic Jump Location
Variation of equivalent plastic strain, εe, along the PTH/dielectric interface in the clearance hole region for cases without and with inner plane connections for a ΔT of 102°C
Grahic Jump Location
Variation of normal (peel) stress, σrr, along the PTH/dielectric (and IP) interface in the clearance hole region for cases without and with inner plane connections for a ΔT of 102°C

Tables

Errata

Discussions

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In