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TECHNICAL BRIEFS

Lead-On-Chip Versus Chip-On-Lead Packages and Solder Failure Criteria

[+] Author and Article Information
Boris Mirman

Weidlinger Associates Inc, Consulting Engineers, One Broadway, 11th Floor, Cambridge MA 02142-1100

J. Electron. Packag 122(3), 279-280 (Jan 09, 2000) (2 pages) doi:10.1115/1.1286105 History: Received July 09, 1998; Revised January 09, 2000
Copyright © 2000 by ASME
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References

Figures

Grahic Jump Location
Bowing of free TSOPs under cooling
Grahic Jump Location
Directions of forces and moments applied to TSOP’s leads

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