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TECHNICAL PAPERS

Reliability Analysis of Flip Chip Designs Via Computer Simulation

[+] Author and Article Information
Hua Lu, C. Bailey, M. Cross

School of Computing and Mathematical Sciences, The University of Greenwich, 30 Park Row, London SE10 9LS, United Kingdom

J. Electron. Packag 122(3), 214-219 (Jan 17, 2000) (6 pages) doi:10.1115/1.1286122 History: Received August 03, 1999; Revised January 17, 2000
Copyright © 2000 by ASME
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References

Figures

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(a) A model showing a quarter of a typical flip chip. Some underfill fillet and the die have been removed to reveal the solder joints. (b) A top view of a flipchip. The corner solder joints are represented by circles and the shaded area is the part that is needed in the modeling.
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The solder joint structure of (a) Model A and (b) Model B. Materials are represented by different gray scales.
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(a) The distribution of εsumcr in the solder of the corner solder joint and (b) the maximum value of εsumcr as a function of time during a complete thermal cycle
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The maximum εsumcr (○) and Nf (+) versus E of the underfill. The results in (a) are for Model A and that in (b) are for Model B.
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The maximum εsumcr (○) and Nf (+) versus the CTE of the underfill. The results in (a) are for Model A and that in (b) are for Model B.
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The maximum εsumcr (○) and Nf (+) as functions of CTE and E of the underfill. The results in (a) are for Model A and that in (b) are for Model B.
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The maximum εsumcr (○) and Nf (+) versus the standoff height, for Model B
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The maximum εsumcr (○) and Nf (+) versus the thickness of the substrate, for Model A in (a) and Model B in (b)
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The distortion of the corner solder joint of Model B under a thermal load of 150°C. (a): With microvia, (b) without microvia. Significantly greater distortion is observed in the model with microvia.
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The reliability and the out-of-plane CTE of the aramid layer of the substrate

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