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TECHNICAL PAPERS

Fatigue Life Analysis of Solder Joints in Flip Chip Bonding

[+] Author and Article Information
Yutaka Tsukada, Hideo Nishimura

Yasu Technology Application Laboratory, IBM, 800 Ichimiyake, Yasu-cho, Yasu-gun, Shiga-ken 520-23 Japan

Masao Sakane, Masateru Ohnami

Department of Mechanical Engineering, Faculty of Science and Engineering, Ritsumeikan University, 1916 Noji-cho, Kusatsu-shi, Shiga-ken 525 Japan

J. Electron. Packag 122(3), 207-213 (Nov 01, 1999) (7 pages) doi:10.1115/1.1286002 History: Received November 01, 1997; Revised November 01, 1999
Copyright © 2000 by ASME
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References

Nakano, F., Soga, T., and Amagi, S., 1987, “Resin-Insertion Effect on Thermal Cycle Resistivity of Flip-Chip Mounted LSI Devices,” Proceedings of ISHM’87, pp. 536–541.
Suryanarayana, D., Hsiao, R., Gall, P., and Mcreary, M., 1990, “Flip-Chip Solder Bump Fatigue Life Enhanced by Polymer Encapsulation,” Proceedings of 40th ECTC, Vol. 1, pp. 338–344.
Tsukada, Y., Mashimoto, Y., Nishio, T., and Mii, N., 1992, “Reliability and Stress Analysis of Encapsulated Flip Chip Joint on Epoxy Base Printed Circuit Board,” Proceedings of ASME/JSME Joint Conference for Advanced in Electronics Packaging, 2 , pp. 827–835.
O’Malley,  G., Giesler,  J., and Machuga,  S., 1994, “The Importance of Material Selection for Flip Chip on Board Assemblies,” IEEE Trans. Compon., Packag. Manuf. Technol., Part B, 17, No. 3, pp. 248–255.
Giesler,  J., O’Malley,  G., Williams,  M., and Machuga,  S., 1994, “Flip Chip on Board Connection Technology: Process Characterization and Reliability,” IEEE Trans. Compon., Packag. Manuf. Technol., Part B, 17, No. 3, pp. 256–263.
Lau,  J., Krulevitch,  T., Schar,  W., Heydinger,  M., Erasmus,  S., and Gleason,  J., 1993, “Experimental and Analytical Studies of Encapsulated Flip Chip Solder Bumps on Surface Laminar Circuit Boards,” Circuit World, 19, No. 3, pp. 12–24.
Mukai, M., Kawakami, T., Endoh, T., Hiruta, Y., and Takahashi, K., 1994, “Elastic-Creep Thermal Stress Analysis for the SMT-PGA Package’s Solder Joint,” AMD Vol. 187, Mechanics and Material for Electronic Packaging: Vol. 2—Thermal and Mechanical Behavior and Modeling, ASME, pp. 197–203.
Senjyu Metal Industry Co., 1985, “Soldering Manual,” A-01-87, SMIC Technical Bulletin, p. 6.
Yamamoto, T., Sakane, M., Tsukada, Y., and Nishimura, H., 1995, “Multiaxial Creep Fatigue of 63Sn-37Pb Solder at Elevated Temperature, Proceedings of the 33rd Symposium on Strength of Materials at High Temperatures,” ASME, pp. 51–55.

Figures

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Flip chip bonding cross section
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Shape and dimensions of test chip
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Shape and dimensions of test carrier
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Flow of building test sample
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Shape and dimensions of solder joint
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Four-points D.C. potential measurement
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Stress test results in cumulative failure rate
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Joint resistance increase. (a) Encapsulated; (b) unencapsulated
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3D diagram of resistance change. (a) Encapsulated; (b) unencapsulated
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Photographs of failed joints. (a) Encapsulated; (b) magnified; (c) unencapsulated
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3D models used for FEM analysis. (a) Unencapsulated; (b) unencapsulated—full joint; (c) encapsulated—single joint; (d) joint for analysis
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Package deformation. (a) Encapsulated; (b) unencapsulated
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Maximum Mises strain in d18 joint
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Variation of Mises strain with distance from chip center. (a) Encapsulated; (b) unencapsulated
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Mises strain distribution. (a) Encapsulated; (b) unencapsulated
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Relationship between Mises strain amplitude and stress cycles

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