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TECHNICAL PAPERS

A Numerical Study of the Thermal Performance of a Tape Ball Grid Array (TBGA) Package

[+] Author and Article Information
Sanjeev B. Sathe

Microelectronics Division, IBM Corporation, Endicott, NY 13760

Bahgat G. Sammakia

T. J. Watson School of Engineering, SUNY at Binghamton, Binghamton, NY 13902-6000

J. Electron. Packag 122(2), 107-114 (Oct 01, 1999) (8 pages) doi:10.1115/1.483141 History: Received April 01, 1998; Revised October 01, 1999
Copyright © 2000 by ASME
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References

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Guenin,  B. M., Marrs,  R. C., and Molnar,  R. J., 1995, “Analysis of a Thermally Enhanced Ball Grid Array Package,” IEEE Trans. Compon., Packag. Manuf. Technol., Part A, 18, No. 4, pp. 749–757.
Chyu, M. K., and Aghazadeh, A., 1997, “Modeling and Measurements of Heatspreader Thermal Performance in Molded Plastic Packages,” Cooling Technology for Electronic Equipment, W. Aung, ed., Hemisphere Publishing, Washington, DC, pp. 781–793.
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Wroblewski,  D., and Joshi,  Y., 1993, “Computations of Liquid Immersion Cooling for a Protruding Heat Source in a Cubical Enclosure,” Int. J. Heat Mass Transf., 36, pp. 1201–1218.
Joshi,  Y., Haukenes,  L. O., and Sathe,  S., 1993, “Natural Convection in a Rectangular Enclosure Due to a Flush Heat Source Mounted on a Vertical Surface,” Int. J. Heat Mass Transf., 36, pp. 249–263.
Wroblewski,  D., and Joshi,  Y., 1992, “Transient Natural Convection From a Leadless Chip Carrier in a Liquid Filled Enclosure: A Numerical Study,” ASME J. Electron. Packag., 114, pp. 271–279.
Gebhart, B., Jaluria, Y., Mahajan, R. L., and Sammakia, B. G., 1988, Buoyancy-Induced Flows and Transport, Reference Edition, Hemisphere Publishing, Washington DC.
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Reynolds,  S. D., Sammakia,  B. G., and Carden,  T. F., 1992, “Thermal Enhancements for a Thin Film Chip Carrier,” IEEE Trans. Compon., Hybrids, Manuf. Technol., 15, No. 5, Oct. pp.699–706.
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Figures

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A schematic diagram of the TBGA module showing the chip, the card, the cover plate and the stiffener
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(a) Schematic diagram showing the model and the coordinate system; (b) schematic diagram for the C4/solder ball model development
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Schematic diagram showing the location of thermocouples used in the experimental study. The chip junction temperature was measured by using a calibrated resistor on the specially designed thermal chip.
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Schematic diagram showing the automatic data acquisition system (TDAQ)
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Schematic diagram showing the thermal test section used for the TBGA tests
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Chip junction temperatures as a function of incoming air velocities. Numerical results are shown for a card with 0, 1, and 2 power planes. Also shown are experimental measurements for a card with two power planes.
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Chip junction temperatures as a function of chip power levels in natural convection. Numerical results are shown for a card with 0, 1, and 2 power planes. Effect of no radiation is shown for a card with 2 power planes.
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Temperature distributions at the centerline of the card and package. Results are shown for a 3 in.×3 in., 2 power plane card with a chip power of 4 W.
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Temperature distributions at the centerline of the card and package. Results are shown for three incoming air flow velocities: 0, 0.36, and 0.81 m/s for a 3 in.×3 in. card with no power planes. Chip power=4 W.
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Temperature distributions at the center line of the card and module. Results are shown for 3 in.×3 in. cards with 0, 1 and 2 power planes. All results are shown for an incoming area flow velocity of 0.81 m/s and chip power=4 W.
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Temperature contours along the centerline of the card and module for a chip power dissipation of 6 W, under natural convection. The card under consideration has two power planes. There are 5 contours spaced equally from 25°C to 98°C.
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Temperature contours along the centerline of the card and module for a chip power of 6 W under natural convection. The card under consideration has no power planes. There are 5 equispaced contours from 25°C to 136°C.
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Velocity vectors in the vicinity of the module and 3 in.×3 in. card with 2 power planes. The results are shown at the center line of the card and module at a chip power of 6 W under natural convection.
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The effect of interconnect thermal conductivity on the chip junction temperature

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