0
TECHNICAL PAPERS

A Numerical Study of the Thermal Performance of a Tape Ball Grid Array (TBGA) Package

[+] Author and Article Information
Sanjeev B. Sathe

Microelectronics Division, IBM Corporation, Endicott, NY 13760

Bahgat G. Sammakia

T. J. Watson School of Engineering, SUNY at Binghamton, Binghamton, NY 13902-6000

J. Electron. Packag. 122(2), 107-114 (Oct 01, 1999) (8 pages) doi:10.1115/1.483141 History: Received April 01, 1998; Revised October 01, 1999
Copyright © 2000 by ASME
Your Session has timed out. Please sign back in to continue.

References

Figures

Grahic Jump Location
A schematic diagram of the TBGA module showing the chip, the card, the cover plate and the stiffener
Grahic Jump Location
(a) Schematic diagram showing the model and the coordinate system; (b) schematic diagram for the C4/solder ball model development
Grahic Jump Location
Schematic diagram showing the location of thermocouples used in the experimental study. The chip junction temperature was measured by using a calibrated resistor on the specially designed thermal chip.
Grahic Jump Location
Schematic diagram showing the automatic data acquisition system (TDAQ)
Grahic Jump Location
Schematic diagram showing the thermal test section used for the TBGA tests
Grahic Jump Location
Chip junction temperatures as a function of incoming air velocities. Numerical results are shown for a card with 0, 1, and 2 power planes. Also shown are experimental measurements for a card with two power planes.
Grahic Jump Location
Chip junction temperatures as a function of chip power levels in natural convection. Numerical results are shown for a card with 0, 1, and 2 power planes. Effect of no radiation is shown for a card with 2 power planes.
Grahic Jump Location
Temperature distributions at the centerline of the card and package. Results are shown for a 3 in.×3 in., 2 power plane card with a chip power of 4 W.
Grahic Jump Location
Temperature distributions at the centerline of the card and package. Results are shown for three incoming air flow velocities: 0, 0.36, and 0.81 m/s for a 3 in.×3 in. card with no power planes. Chip power=4 W.
Grahic Jump Location
Temperature distributions at the center line of the card and module. Results are shown for 3 in.×3 in. cards with 0, 1 and 2 power planes. All results are shown for an incoming area flow velocity of 0.81 m/s and chip power=4 W.
Grahic Jump Location
Temperature contours along the centerline of the card and module for a chip power dissipation of 6 W, under natural convection. The card under consideration has two power planes. There are 5 contours spaced equally from 25°C to 98°C.
Grahic Jump Location
Temperature contours along the centerline of the card and module for a chip power of 6 W under natural convection. The card under consideration has no power planes. There are 5 equispaced contours from 25°C to 136°C.
Grahic Jump Location
Velocity vectors in the vicinity of the module and 3 in.×3 in. card with 2 power planes. The results are shown at the center line of the card and module at a chip power of 6 W under natural convection.
Grahic Jump Location
The effect of interconnect thermal conductivity on the chip junction temperature

Tables

Errata

Discussions

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In