0
TECHNICAL PAPERS

A Study on Warpage of Flexible SS Substrates for Large Area MCM-D Packaging

[+] Author and Article Information
Anh X. H. Dang, I. Charles Ume

School of Mechanical Engineering, Georgia Institute of Technology, 813 Ferst Drive, Atlanta, GA 30332

Swapan K. Bhattacharya

Packaging Research Center, Georgia Institute of Technology, 813 Ferst Drive, Atlanta, GA 30332

J. Electron. Packag 122(2), 86-91 (Dec 29, 1999) (6 pages) doi:10.1115/1.483152 History: Received June 01, 1999; Revised December 29, 1999
Copyright © 2000 by ASME
Your Session has timed out. Please sign back in to continue.

References

Tummala, R. R., Nandakumar, G. A., Bolda, F., and Klopfenstein, A., 1997, Microelectronic Packaging Handbook, Chap. 18, Chapman & Hall, London.
Padmadinata,  F. Z., Veerhoek,  J. J., Van Dijk,  G. J. A., and Huijsing,  J. H., 1990, “Microelectronic Skin Electrode,” Sens. Actuators B, B1, pp. 491–49.
Dang, A., Ume, I. C., and Bhattacharya, S., 1999, “In-Situ Warpage Measurement during Thermal Cycling of Dielectric Coated SS Substrates,” ASME Conference, Tennessee. The ASME International Mechanical Engineering Conference and Exposition, November 14–19, 1999, Nashville, TN.
Southerlin, S., Polsky, Y., and Ume, C., 1998, “Relative Comparison of PWB Warpage Due to Simulated Infrared and Wave Soldering Processes,” Proceedings 48th IEEE Electronic Components and Technology Conference, pp. 807–815.
Polsky, Y., Ume, C., and Southerlin, W., 1998, “Application of Thermoelastic Lamination Theory to Predict Warpage of a Symmetric and Simply Supported PWB During Temperature Cycling,” Proceedings 48th IEEE Electronic Components and Technology Conference, pp. 345–352.
Polsky, Y., Southerlin, W., and Ume, C., 2000, “A Comparison of PWB Warpage Due to Simulated Infrared and Wave Soldering Processes,” IEEE, CPMT, Part C (accepted for publication).
Martin, T., Yeh, C., and Ume, C., 1991, “Measurement of Thermally Induced Warpage in Printed Wiring Boards,” Manufacturing Processes and Materials Challenges in Microelectronic Packaging, 131 , Conference Proceedings, ASME, New York, pp. 43–47.
Yeh, C., Ume, C., Martin, T., and Fulton, B., 1991, “Correlation of Analytical and Experimental Approaches to Thermo-Mechanical Design,” American Society of Mechanical Engineers, Winter Annual Meeting, Atlanta, pp. 1–9.
Yeh, C., Banerjee, K., Martin, T., Umeagukwu, C., Stafford, J., and Wyatt, K., 1991, “Experimental and Analytical Investigation of Thermally Induced Warpage for Printed Wiring Boards,” Proceedings IEEE Electronic Components Conference, pp. 382–387.
Yeh,  C., Ume,  C., Fulton,  R., Wyatt,  K., and Stafford,  J., 1993, “Correlation of Analytical and Experimental Approaches to Determine Thermally Induced PWB Warpage,” IEEE Trans. Compon., Hybrids, Manuf. Technol., 16, pp. 986–995.
Zewi, I., Daniel, I., and Gotro, J., 1985, “Residual Stresses and Warpage in Circuit Board Composite Laminates,” Proceedings 1985 SEM Fall Conference on Experimental Mechanics: Transducer Technology for Physical Measurements, Grenelefe, FL, pp. 19–26.
Post, D., Han, B., and Ifju, P., 1994, High Sensitivity Moire, Springer-Verlag, New York.
Liu, S., Qian, Z., and Yeh, C. P., (editors), 1998, Proceedings of the 1998 ASME International Mechanical Engineering Congress and Exposition, Anaheim, CA.
Han, B., Guo, Y., and Choi, H., 1993, “Out-of-Plane Displacement Measurement of Printed Circuit Board by Shadow Moire With Variable Sensitivity,” Advances in Electronic Packaging, ASME EEP, 4-1 , pp. 179–185.
Wang, Y., and Hassel, P., (editors), 1998, “Measurement of a Thermally Induced Deformation of a BGA Using Phase-Stepping Shadow Moire,” Experimental/Numerical Mechanics in Electronic Packaging, 2 , pp. 32–39.
Wang,  Y., and Hassel,  P., 1998, “On-line Measurement of a Thermally Induced Warpage of a BGA with a High Sensitive Shadow Moire,” Int. J. Microcircuit Electron. Packag., 21, No. 2, pp. 191–196.
Stitler,  M. R., and Ume,  I. C., 1997, “System for Real-Time Measurement of Thermally Induced PWB/PWA Warpage,” ASME J. Electron. Packag., 119, pp. 1–77.
Stitler,  M. R., Ume,  I. C., and Leutz,  B., 1996, “In Process Board Warpage Measurement in a Lab Scale Wave Soldering Oven,” IEEE Trans. Compon., Packag. Manuf. Technol., Part A, 19, pp. 562–569.

Figures

Grahic Jump Location
Cross-section of filled via
Grahic Jump Location
Three-dimensional warpage data plot and discrete data locations
Grahic Jump Location
SS Sample 1, as received, at room temperature: (a) Moiré phased image; (b) point values; (c) three-dimensional surface plot
Grahic Jump Location
SS Sample 1, post parylene coating, at room temperature: (a) Moiré phased image; (b) point values; (c) three-dimensional surface plot
Grahic Jump Location
SS Sample 1, post via-fill, at room temperature: (a) Moiré phased image; (b) point values; (c) three-dimensional surface plot
Grahic Jump Location
Schematic of shadow Moiré setup
Grahic Jump Location
Simulated infrared reflow on-line measurement system
Grahic Jump Location
AFM images of the dielectric coated SS surface topology
Grahic Jump Location
AFM images of the dielectric coated SS surface roughness
Grahic Jump Location
Cracking of parylene film, 50X
Grahic Jump Location
Filled 0.01 inch diameter vias

Tables

Errata

Discussions

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In