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TECHNICAL PAPERS

Thermoelastic Modeling of a PWB With Simulated Circuit Traces Subjected to Infrared Reflow Soldering With Experimental Validation

[+] Author and Article Information
Y. Polsky, I. C. Ume

School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0405

J. Electron. Packag 121(4), 263-270 (Dec 01, 1999) (8 pages) doi:10.1115/1.2793850 History: Received January 01, 1999; Revised May 05, 1999; Online November 05, 2007

Abstract

A bare, four copper layer printed wiring board with simple trace patterns was built for modeling and experimental validation purposes. In-plane elastic properties of the core materials in the board were measured as a function of temperature. Thermoelastic lamination theory was utilized to predict the warpage of the board when subjected to an infrared reflow process, with emphasis on studying the influence of thermal gradients through the board, its support conditions and CTE differential on the warpage process. Board layers with traces were approximated with quasi-homogeneous effective properties obtained using micromechanics theory. An experimental system that employs the shadow moird technique in a simulated infrared reflow environment was used to evaluate the warpage for comparison to modeled results.

Copyright © 1999 by The American Society of Mechanical Engineers
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