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TECHNICAL PAPERS

Thermomechanical Finite Element Analysis of Problems in Electronic Packaging Using the Disturbed State Concept: Part 2—Verification and Application

[+] Author and Article Information
C. Basaran

Department of Civil Engineering, SUNY at Buffalo, Buffalo, NY 14260

C. S. Desai, T. Kundu

Department of Civil Engineering and Engineering Mechanics, University of Arizona, Tucson, AZ 85718

J. Electron. Packag 120(1), 48-53 (Mar 01, 1998) (6 pages) doi:10.1115/1.2792285 History: Received November 10, 1995; Revised May 30, 1997; Online November 06, 2007

Abstract

The finite element procedure with the unified disturbed state modeling concept presented in Part I, Basaran et al. (1998), is verified here with respect to laboratory test results for Pb40/Sn60 eutectic solder alloy. This solder alloy is a commonly used interconnection material for surface mount technology packages. It is demonstrated that the proposed procedure provides highly satisfactory correlation with the observed laboratory behavior of materials and with test results for a chip-substrate system simulated in the laboratory.

Copyright © 1998 by The American Society of Mechanical Engineers
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