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RESEARCH PAPERS

Thermal Strain Measurements of Solder Joints in Second Level Interconnections Using Moire Interferometry

[+] Author and Article Information
Yifan Guo, Charles G. Woychik

Technology Laboratory, IBM Corporation, Endicott, NY 13760

J. Electron. Packag 114(1), 88-92 (Mar 01, 1992) (5 pages) doi:10.1115/1.2905446 History: Received June 30, 1991; Revised January 05, 1992; Online April 28, 2008

Abstract

Low cycle fatigue of solder joints is one of the major kinds of failures in second level interconnections of an electronic package. The fatigue failure is caused by thermal strains which are created from a mismatch of coefficients of thermal expansion (CTE) that occurs between two levels of packaging. As the package approaches smaller dimensions, measurements of thermal strains in the solder interconnections become very difficult. In this paper, moire interferometry technique was applied to evaluate the thermal strains in the second level interconnections for both conventional pin-in-hole (PIH) packages and surface mount components. The coefficient of thermal expansion of each component was measured. Thermal strain distributions in the solder interconnections were determined, and reliability issues were discussed. The strains in solder joints of the PIH components were much higher than those of the stacked surface mount components. Even though the surface mount components had a lower inherent strength, their overall mechanical reliability was much higher since they had practically no localized strain concentrations.

Copyright © 1992 by The American Society of Mechanical Engineers
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