Design Factors With Realistic I/O Distributions

[+] Author and Article Information
John P. Koons

IBM Corporation, Endicott, NY 13760

J. Electron. Packag 113(1), 76-80 (Mar 01, 1991) (5 pages) doi:10.1115/1.2905370 History: Revised January 10, 1991; Online April 28, 2008


This paper explores some design factors, including wireability, of packages in which the number of I/O per module to be interconnected varies widely. This is of interest because it is common for memory card designs and for work station and personal computer printed circuit designs. Memory cards often have a few relatively high pin count control logic modules supporting many low pin count array modules. Work station and personal computer cards often use low density “glue” logic modules with a few microprocessor modules and their high function supports. Printed circuit cost and performance factors are examined by example. Differences between area array and perimeter escape components and leverage possibilities of multi-chip modules are examined. A background tutorial on wireability analysis is given. The algorithm used was developed by Wadie Mikhail several years ago. Analyses are based on the length of wire paths available in a given design, the length of wire needed and the utilizations of the available paths. Utilization guidelines are suggested. Alternative wireability algorithms are identified and briefly discussed. Although the examples are given for cases of modules on cards, the methodologies and general conclusions are valid at other packaging levels; for example, for chips on multi-chip modules.

Copyright © 1991 by The American Society of Mechanical Engineers
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