Thermal Stress CAD Analysis of a Multi-Layer Composite of an Operating Transistor Package

[+] Author and Article Information
Agha J. Ghorieshi, Umid R. Nejib

School of Science and Engineering, Wilkes University, Wilkes-Barre, PA 18766

J. Electron. Packag 112(1), 77-80 (Mar 01, 1990) (4 pages) doi:10.1115/1.2904345 History: Received January 03, 1990; Online April 28, 2008


Thermal stress management is a major factor in the design of an electronic package. Thermal mismatch among the assembled components induces thermal stresses within the device. Finite element technique is utilized for three dimensional thermal stress analysis of a transistor with a free convection cooling system. Heat transfer analysis is used to determine the temperature distribution throughout the package for a given operating temperature. The data are then used to determine package stresses. The results show the shear stress concentration is higher at the corner of the chip. These values were found to be lower compared to those using temperature cycle analysis. An alternative method of lowering shear stresses in the chip is suggested.

Copyright © 1990 by The American Society of Mechanical Engineers
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