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Research Papers

Experimental Characterization of the Vertical and Lateral Heat Transfer in Three-Dimensional Stacked Die Packages

[+] Author and Article Information
Herman Oprins

IMEC,
Kapeldreef 75,
Leuven B-3001, Belgium
e-mail: oprins@imec.be

Vladimir Cherman

IMEC,
Kapeldreef 75,
Leuven B-3001, Belgium
e-mail: vladimir.cherman@imec.be

Geert Van der Plas

IMEC,
Kapeldreef 75,
Leuven B-3001, Belgium
e-mail: geert.vanderplas@imec.be

Joeri De Vos

IMEC,
Kapeldreef 75,
Leuven B-3001, Belgium
e-mail: joeri.devos@imec.be

Eric Beyne

IMEC,
Kapeldreef 75,
Leuven B-3001, Belgium
e-mail: eric.beyne@imec.be

1Corresponding author.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received September 25, 2015; final manuscript received December 17, 2015; published online March 10, 2016. Assoc. Editor: Satish Chaparala.

J. Electron. Packag 138(1), 010902 (Mar 10, 2016) (10 pages) Paper No: EP-15-1090; doi: 10.1115/1.4032346 History: Received September 25, 2015; Revised December 17, 2015

In this paper, we present the experimental characterization of three-dimensional (3D) packages using a dedicated stackable test chip. An advanced complementary metal oxide silicon (CMOS) test chip with programmable power distribution has been designed, fabricated, stacked, and packaged in molded and bare die 3D packages. The packages have been experimentally characterized in test sockets with and without cooling and soldered to the printed circuit board (PCB). Using uniform and localized hot spot power distribution, the thermal self-heating and thermal coupling resistance and the lateral spreading in the 3D packages have been studied. Furthermore, the measurements have been used to characterize the thermal properties of the die–die interface and to calibrate a thermal model for the calculation of equivalent properties of underfilled μbump arrays. This model has been applied to study the tradeoff between the standoff height reduction and the underfill thermal conductivity increase in order to reduce the interdie thermal resistance.

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Figures

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Fig. 1

Schematic of the PTCQ test chip layout. Left: Overview of the organization of different cells in the chip. Right: Layout detail of the #2 cells with heater elements.

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Fig. 2

Schematic of the 3D-SIC packages

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Fig. 3

Measurement configurations: (a) plastic socket mimicking low-power applications, (b) socket with heat sink and fan for high power applications, and (c) molded and exposed packages soldered to the test board

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Fig. 4

Normalized temperature measurements for quasi-uniform power dissipation in the molded packaged in the low power socket

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Fig. 5

Temperature profiles for quasi-uniform power dissipation in the molded packages in the low power socket

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Fig. 6

Normalized temperature measurements for quasi-uniform power dissipation in the bare die packaged in the high power socket

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Fig. 7

Temperature profiles for quasi-uniform power dissipation in the bare packages in the high power socket

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Fig. 8

Power-normalized temperature profiles for the molded package soldered to PCB for natural convection cooling

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Fig. 9

Normalized temperature measurement profiles for a 2 × 2 array hot spot (480 × 480 μm2) in the soldered bare die 3D package in natural convection conditions

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Fig. 10

Power distribution and temperature measurement for memory on logic low power emulator

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Fig. 11

Temperature profiles for the memory and logic chips in the high power emulator

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Fig. 12

Left: Interdie thermal resistance map Rdd (K/W) for the full chip size (32 × 32 cells). Right: Schematic of the location of μbumps (6 × 6 array per cell) in the die–die interface and Cu pillars in the bottom die–package substrate interface (two pillars on the diagonal per cell) for a 1/16 part of the chip size (8 × 8 cells).

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Fig. 13

Thermal unit cell model for the calculation of equivalent in-plane and out-of-plane thermal conductivity of underfill μbump arrays

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Fig. 14

Impact of the standoff height (a) and the underfill thermal conductivity (b) on the interdie thermal resistance. The marker indicates the situation of the measured 3D PTCQ package.

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