Review Article

Overview and Outlook of Three-Dimensional Integrated Circuit Packaging, Three-Dimensional Si Integration, and Three-Dimensional Integrated Circuit Integration

[+] Author and Article Information
John H. Lau

Fellow ASME
ASM Pacific Technology,
16-22 Kung Yip Street,
Kwai Chung, NT, Hong Kong

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received July 27, 2014; final manuscript received September 11, 2014; published online October 15, 2014. Assoc. Editor: Kyoung-sik Moon.

J. Electron. Packag 136(4), 040801 (Oct 15, 2014) (15 pages) Paper No: EP-14-1068; doi: 10.1115/1.4028629 History: Received July 27, 2014; Revised September 11, 2014

3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC integration. They are different and in general the through-silicon via (TSV) separates 3D IC packaging from 3D Si/IC integrations since the latter two use TSV but 3D IC packaging does not. 3D Si integration and 3D IC integration are different. 3D IC integration stacks up the thin chips with TSV and microbump, while 3D Si integration stacks up thin wafers with TSV alone (i.e., bumpless). TSV is the heart of 3D Si/IC integrations and is the focus of this investigation. Also, the state-of-the-art, challenge, and trend of 3D integration will be presented and examined. Furthermore, supply chain readiness for high volume manufacturing (HVM) of TSVs is discussed.

Copyright © 2014 by ASME
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Fig. 1

3D integration technologies versus maturity [2]

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Fig. 2

TSV invented by Shockley (U.S. patent #3,044,909)

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Fig. 3

AMKOR’s 3D IC packaging (stacked chips by Cu wirebonding)

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Fig. 4

3D IC packaging (wirebonding package on flip chip package). Top: schematic, bottom: photo image.

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Fig. 5

3D IC packaging (chip-to-chip interconnects) [137]

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Fig. 6

3D IC packaging (Amkor’s multiple chip-to-chip interconnects) [138]

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Fig. 7

3D IC packaging (STATSChipPAC’s package-on-package) [139]

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Fig. 8

3D Si integration: (a) IBM/RPI’s Cu-to-Cu bonding [90] and (b) NIMS/AIST/Toshiba/University of Tokyo’s Cu-to-Cu bonding [93]

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Fig. 9

3D Si integration: (a) MIT’s oxide-to-oxide bonding [100-106] and (b) LETI/Freescale/STMicroelectronics’ oxide-to-oxide bonding [107,108]

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Fig. 10

Micron’s sample on HMC [140]

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Fig. 11

Intel’s Knights Landing processor unit with Micron’s HMC

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Fig. 12

Schematic of JEDEX’s Wide I/O 2. Pattern of quadrants of microbumps.

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Fig. 13

Schematic of JEDEX/Hynix’s HBM

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Fig. 14

TSV/RDL passive interposer supporting chips on package substrate

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Fig. 15

Altera/TSMC’s CoWoS [42]

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Fig. 16

TSV fabrication process flow

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Fig. 17

SEM images of TSV cross sections [5]

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Fig. 18

Process flow for fabricating RDLs by dual Cu damascene

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Fig. 19

SEM images of cross sections of RDLs fabricated by the Cu damascene method [5]

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Fig. 20

Conventional process flow for chip on interposer wafer on package substrate [8]

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Fig. 21

Backside Cu reveal and UBM/solder plating process flow

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Fig. 22

TSV Cu revealing. (Left) Before dry etch of Si. (Right) After Si dry etching, low-temperature SiN/SiO2, and removal (CMP) of the isolation, barrier, and seed layer [5].




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