Research Papers

Four-Wire Bridge Measurements of Silicon van der Pauw Stress Sensors

[+] Author and Article Information
Richard C. Jaeger

Electrical Engineering Department,
Alabama Micro/Nano Science
and Technology Center,
Auburn University,
Auburn, AL 36849
e-mail: rj@jaegerengineering.com

Mohammad Motalab, Safina Hussain, Jeffrey C. Suhling

Mechanical Engineering Department,
Center for Advanced Vehicle and Extreme
Environment Electronics (CAVE3),
Auburn University,
Auburn, AL 36849

We refer to these as van der Pauw sensors since the stress sensor output is directly related to van der Pauw’s original voltage and resistivity results.

Often expressed in terms of infinite series.

Or between any two symmetrically located points on opposite sides of the device.

Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received March 2, 2014; final manuscript received August 15, 2014; published online September 19, 2014. Assoc. Editor: Satish Chaparala.

J. Electron. Packag 136(4), 041014 (Sep 19, 2014) (10 pages) Paper No: EP-14-1027; doi: 10.1115/1.4028333 History: Received March 02, 2014; Revised August 15, 2014

Under the proper orientations and excitations, the transverse output of rotationally symmetric four-contact van der Pauw (VDP) stress sensors depends upon only the in-plane shear stress or the difference of the in-plane normal stresses on (100) silicon. In bridge-mode, each sensor requires only one four-wire measurement and produces an output voltage with a sensitivity that is 3.16 times that of the equivalent resistor rosettes or bridges, just as in the normal VDP sensor mode that requires two separate measurements. Both numerical and experimental results are presented to validate the conjectured behavior of the sensor. Similar results apply to sensors on (111) silicon. The output voltage results provide a simple mathematical expression for the offset voltage in Hall effect devices or the response of pseudo Hall-effect sensors. Bridge operation facilitates use of the VDP structure in embedded stress sensors in integrated circuits.

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Mason, W. P., and Thurston, R. N., 1957, “Use of Piezoresistive Materials in the Measurement of Displacement, Force and Torque,” J. Acoust. Soc. Am., 29(10), pp. 1096–1101. [CrossRef]
Pfann, W. G., and Thurston, R. N., 1961, “Semiconducting Stress Transducers Utilizing the Transverse and Shear Piezoresistance Effects,” J. Appl. Phys., 32(10), pp. 2008–2019. [CrossRef]
Samaun, S., Wise, K., Nielsen, E., and Angell, J., 1971, “An IC Piezoresistive Pressure Sensor for Biomedical Instrumentation,” IEEE International Solid-State Circuits Conference, Philadelphia, PA, Feb 17–19, pp. 104–105. [CrossRef]
Kanda, Y., and Yasukawa, A., 1982, “Hall-Effect Devices as Strain and Pressure Sensors,” Sens. Actuators, 2, pp. 283–296. [CrossRef]
Zhadko, I. P., Babichev, G. G., Kozlovskiy, S. I., Romanov, V. A., Sharan, N. N., and Zinchenko, E. A., 2001, “Silicon Pressure Transducer With Differential Element Based on the Transverse Electromotive Force Effect,” Sens. Actuators A, 90(1–2), pp. 89–95. [CrossRef]
Barlian, A. A., Park, W.-T., Mallon, J. R., Rastegar, A. J., and Pruitt, B. L., 2009, “Review: Semiconductor Piezoresistance for Microsystems,” Proc. IEEE, 97(3), pp. 513–552. [CrossRef]
Gridchin, A. V., and Gridchin, V. A., 1997, “The Four-Terminal Piezotransducer: Theory and Comparison With the Piezoresistive Bridge,” Sens. Actuators A: Phys., 58(3), pp. 219–223. [CrossRef]
Kanda, Y., and Migitaka, M., 1976, “Effect of Mechanical Stress on the Offset Voltages of Hall Devices in Si IC,” Phys. Status Solidi A, 35(2), pp. k115–k118. [CrossRef]
Steiner, R., Maier, C., Bellekom, S., and Baltes, H., 1999, “Influence of Mechanical Stress on the Offset Voltages of Hall Devices Operated With Spinning Current Method,” J. MEMS, 8(4), pp. 466–472. [CrossRef]
Rise, O., Shaked, E., Karpovsky, M., and Gerber, A., 2008, “Offset Reduction in Hall Effect Measurements Using a Nonswitching van der Pauw Technique,” Rev. Sci. Instrum., 79(7), p. 073901. [CrossRef] [PubMed]
Bartholomeyczik, J., Doelle, M., Ruther, P., and Paul, O., 2009, “Cartesian Lattice Spinning Current Method for the Simple Extraction of σxxyy and σxy Stresses and the Hall Voltage From Four-Contact Elements,” 13th International Conference on Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS'05), New York, June 5–9, pp. 2127–2130. [CrossRef]
Spencer, J. L., Schroen, W. H., Bednarz, G. A., Bryan, J. A., Metzgar, T. D., Cleveland, R. D., and Edwards, D. R., 1981, “New Quantitative Measurements of IC Stress Introduced by Plastic Packages,” 19th IEEE Annual Reliability Physics Symposium, Las Vegas, NV, Apr. 7–9, pp. 74–80. [CrossRef]
Gee, S. A., van den Bogert, W. F., and Akylas, V. R., 1989, “Strain-Gauge Mapping of Die Surface Stresses,” IEEE Trans. Comp., Hybrids, Manuf. Technol., 12(4), pp. 587–593. [CrossRef]
Bittle, D. A., Suhling, J. C., Beaty, R. E., Jaeger, R. C., and Johnson, R. W., 1991, “Piezoresistive Stress Sensors for Structural Analysis of Electronic Packages,” ASME J. Electron. Packag., 113(3), pp. 203–215. [CrossRef]
Sweet, J. N., 1993, “Die Stress Measurement Using Piezoresistive Stress Sensors,” Thermal Stress and Strain in MicroelectronicsPackaging, J. H.Lau, ed., von Nostrand Reinhold, New York, pp. 221–271.
Gestel, R. V., 1994, Reliability Related Research on Plastic IC Packages: A Test Chip Approach, Delft Technical University, Delft, Netherlands.
Zou, Y., Suhling, J. C., Jaeger, R. C., and H.Ali, 1998, “Three Dimensional Die Surface State Measurements in Delaminated and Non-Delaminated Plastic Packages,” 48th IEEE Electronic Components and Technology Conference, Seattle, WA, May 25–28, pp. 1223–1234. [CrossRef]
Zou, Y., Suhling, J. C., Johnson, R. W., Jaeger, R. C., and Mian, A. K. M., 1999, “In-Situ Stress State Characterization During Chip-on-Board Assembly,” IEEE Trans. Electron. Packag. Manuf., 22(1), pp. 38–52. [CrossRef]
Doelle, M., Peters, C., Ruther, P., and Paul, O., 2006, “Piezo-FET Stress Sensor Arrrays for Wire Bonding Characterization,” IEEE J. MEMS, 15(1), pp. 120–130. [CrossRef]
Baumann, M., Gieschke, P., Lemke, B., and Paul, O., 2010, “CMOs Sensor Chip With a 10×10 Array of Unit Cells for Mapping Five Stress Components and Temperature,” IEEE 23rd International Conference Micro Electro Mechancial Systems, (MEMS), Wanchai, Hong Kong, Jan. 24–28, pp. 604–607. [CrossRef]
Chen, Y., Jaeger, R. C., and Suhling, J. C., 2013, “CMOS Sensor Arrays for High Resolution Die Stress Mapping in Packaged Integrated Circuits,” IEEE Sens. J., 13(6), pp. 2066–2076. [CrossRef]
Hamada, T. F., Saito, N., and Takeda, E., 1991, “A New Aspect of Mechanical Stress Effects in Scaled MOS Devices,” IEEE Trans. Electron Devices, 38(4), pp. 895–900. [CrossRef]
Jaeger, R. C., Ramani, R., and Suhling, J. C., 1995, “Effects of Stress-Induced Mismatches on CMOS Analog Circuits,” International Symposium on VLSI Technology, Systems, and Applications, Taipei, Taiwan, May 31–June 2, pp. 354–360. [CrossRef]
Ali, H., 1997, “Stress-Induced Parametric Shift in Plastic Packaged Devices,” IEEE Trans. Comp., Packag. Manuf. Technol., Part B, 20(4), pp. 458–462. [CrossRef]
Bastos, J., Steyaert, M. S. J., Pergoot, A., and Sansen, W. M., 1997, “Influence of Die Attachment on MOS Transistor Matching,” IEEE Trans. Semicond. Manuf., 10(2), pp. 209–218. [CrossRef]
Jaeger, R. C., Bradley, A. T., Suhling, J. C., and Zou, Y., 1997, “FET Mobility Degradation and Device Mismatch Due to Packaging Induced Die Stress,” 23rd European Solid-State Circuits Conference (ESSCIRC'97), Southampton, UK, Sept. 16–18, pp. 272–275.
Tuinhout, H. P., and Vertregt, M., 2001, “Characterization of Systematic MOSFET Current Factor Mismatch Caused by Metal CMP Dummy Structures,” IEEE Trans. Semicond. Manuf., 14(4), pp. 302–310. [CrossRef]
Fruett, F., Meijer, G. C. M., and Bakker, A., 2003, “Minimization of the Mechanical-Stress-Induced Inaccuracy in Bandgap Voltage References,” IEEE J. Solid-State Circuits, 38(7), pp. 1288–1291. [CrossRef]
Jaeger, R. C., Suhling, J. C., Ramani, R., Bradley, A. T., and Xu, J., 2000, “CMOS Stress Sensors on (100) Silicon,” IEEE J. Solid-State Circuits, 35(1), pp. 85–95. [CrossRef]
Bartholomeyczik, J., Brugger, S., Ruther, P., and Paul, O., 2005, “Multidimensional CMOS In-Plane Stress Sensor,” IEEE Sens. J., 5(5), pp. 872–882. [CrossRef]
Baumann, M., Lemke, B., Ruther, P., and Paul, O., 2009, “Piezoresistive CMOS Sensor for Out-of-Plane Shear Stress,” 2009 IEEE Sensors Conference, Christchurch, New Zealand, Oct. 25–28, pp. 441–444. [CrossRef]
Mian, A., Suhling, J. C., Jaeger, R. C., and Wilamowski, B. M., 1997, “Evaluation of Die Stress Using van der Pauw Sensors,” ASME International Mechanical Engineering Congress and Exposition, Dallas, TX, Nov. 16–21, EEP-Vol. 22, pp. 59–67.
Mian, A. K. M., Suhling, J. C., and Jaeger, R. C., 2006, “The van der Pauw Stress Sensor,” IEEE Sens. J., 6(2), pp. 340–356. [CrossRef]
van der Pauw, L. J., 1958, “A Method of Measuring Specific Resistivity and Hall Effect of Disks of Arbitrary Shape,” Philips Res. Rep., 13(1), pp. 1–9, available at: http://aki.issp.u-tokyo.ac.jp/okano/WalWiki/etc/VDP_PRR_13_1.pdf
van der Pauw, L. J., 1961, “Determination of Resistivity Tensor and Hall Tensor of Anisotropic Conductors,” Philips Res. Rep., 16, pp. 187–195.
Bartholomeyczik, J., Kibbel, S., Ruther, P., and Paul, O., 2005, “Extraction of Compensated σxxyy and σxy Stresses From a Single Four-Contact Sensor Using the Spinning Transverse Voltage Method,” 18th IEEE International Conference on Micro Electro Mechanical Systems, 2005 (MEMS 2005), Miami, FL, Jan. 30–Feb. 3, pp. 263–266.
Doelle, M., Mager, D., Ruther, P., and Paul, O., 2006, “Geometry Optimization for Planar Piezoresistive Stress Sensors Based on the Pseudo-Hall Effect,” Sens. Actuators A, 127(2), pp. 261–269. [CrossRef]
Versnel, W., 1979, “Analysis of the Greek Cross, a van der Pauw Structure With Finite Contacts,” Solid-State Electron., 22(11), pp. 911–914. [CrossRef]
Versnel, W., 1981, “Analysis of Symmetrical Hall Plates With Finite Contacts,” J. Appl. Phys., 52(7), pp. 4659–4666. [CrossRef]
Versnel, W., 1982, “The Geometrical Correction Factor for a Rectangular Hall Plate,” J. Appl. Phys., 53(7), pp. 4980–4986. [CrossRef]
Chwang, R., Smith, B. J., and Crowell, C. R., 1974, “Contact Size Effects on the van der Pauw Method for Resistivity and Hall Coefficient Measurement,” Solid-State Electron., 17(12), pp. 1217–1227. [CrossRef]
Koon, D. W., 1989, “Effect of Contact Size and Placement, and of Resistive Inhomogenities on van der Pauw Measurements,” Rev. Sci. Instrum., 60(2), pp. 271–274. [CrossRef]
Suhling, J. C., and Jaeger, R. C., 2001, “Silicon Piezoresistive Stress Sensors and Their Application in Electronic Packaging,” IEEE Sens. J., 1(1), pp. 14–30. [CrossRef]
Smith, C. S., 1953, “Piezoresistance Effects in Germanium and Silicon,” Phys. Rev., 94(1), pp. 42–49. [CrossRef]
Tufte, O. N., and Stelzer, E. L., 1963, “Piezoresistive Properties of Silicon Diffused Layers,” J. Appl. Phys., 34(2), pp. 3322–3327. [CrossRef]
Cordes, R. A., Suhling, J. C., Kang, Y., and Jaeger, R. C., 1995, “Optimal Temperature Compensated Piezoresistive Stress Sensor Rosettes,” Symposium on Applications of Experimental Mechanics to Electronic Packaging, ASME IMECE, AMD-Vol-214, pp. 109–116.
Jaeger, R. C., Suhling, J. C., and Ramani, R., 1994, “Errors Associated With the Design, Calibration and Application of Piezoresistive Stress Sensors in (100) Silicon,” IEEE Trans. CPMT B, 17(1), pp. 97–107. [CrossRef]
Jaeger, R. C., Motalab, M., Hussain, S., and Suhling, J. C., 2013, “Four-Wire Bridge Measurements of van der Pauw Stress Sensors on (100) and (111) Silicon,” ASME Paper No. IPACK2013-73249. [CrossRef]
Mian, A. K. M., 2000, Application of the van der Pauw Structure as a Piezoresistive Stress Sensor, Ph.D. dissertation, Auburn University, Auburn, AL.
Cho, C.-H., Jaeger, R. C., and Suhling, J. C., 2008, “Characterization of the Temperature Dependence of the Piezoresistive Coefficients of Silicon From −150 °C to +125 °C,” IEEE Sens. J., 8(8), pp. 1455–1468. [CrossRef]


Grahic Jump Location
Fig. 1

Square VDP devices at 0 deg and 45 deg orientations. (a) (σ'11-σ'22) sensor and (b) σ'12 sensor. Sensor outputs voltage appear between terminals B and D.

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Fig. 2

Principal and primed coordinate systems for (100) silicon

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Fig. 3

Primed coordinate system for (111) silicon

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Fig. 4

Two versions of four-terminal shear stress sensors

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Fig. 5

The diagonal symmetry line across the square

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Fig. 6

Analysis by superposition: (a) diagonal current excitation and (b) + (c) equivalent circuits for superposition

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Fig. 7

Initial FEA mesh and current excitation I = 100 μA for VDP mode: RVDP = [π/(ln(2)] VDC/IAB

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Fig. 8

Contours of potential distribution for VDP sensor

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Fig. 9

(a) Simulations of the two VDP voltages for 0 deg and 90 deg orientations using the piezoresistive coefficient values in Table 1 for (100) silicon. (b) Simulations of the transverse voltages across the diagonal versus stresses σ'11 and σ'22.

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Fig. 10

Simulated output voltage for the (σ'11-σ'22) stress sensor versus shear stress σ'12 confirming zero response across the diagonal

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Fig. 11

Simulated output of the shear stress sensors versus normal stress σ'11

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Fig. 12

Simulated output of the shear sensor versus shear stress when temperature variations are present

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Fig. 13

Transverse output voltage of the normal stress difference sensor versus normal stress (σ'11-σ'22) when temperature variations are present

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Fig. 14

Simulated output error voltage versus σ'11 for rotational misalignment of a shear stress sensor

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Fig. 15

Microphotograph of a VDP test cell containing 0 deg and 45 deg square n-type and p-type sensors on an n-type substrate. Pads are 100 μm x 100 μm.

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Fig. 16

Measured output of a 0 deg n-type sensor on (111) silicon in bridge mode versus uni-axial stress σ'11

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Fig. 17

Measured output of a 0 deg p-type sensor on (111) silicon in bridge mode versus uni-axial stress σ'11

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Fig. 18

45 deg p-type stress sensor on (111) silicon. (a) Measured transverse output voltage across the sensor showing approximately zero response to σ'11. The worst-case output error is −54 μV. (b) Measured output of the same shear stress sensor in VDP mode versus uni-axial stress σ'11.

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Fig. 19

Measured the transverse voltage output of a 45 deg (111) n-type shear stress sensor versus uni-axial stress showing approximately zero response to σ'11. The maximum output error is 35 μV.




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