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Accepted Manuscripts

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research-article  
X.J. Yao, J.J. Fang and W.J. (Chris) Zhang
J. Electron. Packag   doi: 10.1115/1.4038391
The notion of permeability is very important in understanding and modeling the flow behavior of fluids in a special type of porous medium (i.e., the underfill flow in flip-chip packaging). This paper presents a new concept regarding permeability in a porous medium, namely two types of permeability: superficial permeability (with consideration of both the pore cross-section area and the solid matrix cross-section area) and pore permeability (with consideration of the pore across-section area only). Subsequently, the paper proposes an analytical model (i.e., equation) for the pore permeability and superficial permeability of an underfill porous medium in a flip-chip packaging, respectively. The proposed model along with several similar models in literature is compared with a reliable numerical model developed with the CFD (computational fluid dynamics) technique, and the result of the comparison shows that the proposed model for permeability is the most accurate one among all the analytical models in literature. The main contributions of the paper are: (1) the provision of a more accurate analytical model for the permeability of an underfill porous medium in flip-chip packaging, (2) the finding of two types of permeability depending on how the cross-section area is taken, and (3) the correction of an error in the other's model in literature.
TOPICS: Permeability, Packaging, Flip-chip, Porous materials, Flow (Dynamics), Computational fluid dynamics, Modeling, Errors, Fluids, Computer simulation
Review Article  
Asisa Kumar Panigrahy and Kuan-Neng Chen
J. Electron. Packag   doi: 10.1115/1.4038392
Arguably, the IC industry has received robust scientific and technological attention due to the ultra-small and extremely fast transistors since past four decades that consents to Moore's law. The introduction of new interconnect materials as well as innovative architectures has aided for large scale miniaturization of devices, but their contributions were limited. Thus, the focus has shifted towards the development of new integration approaches that reduce the interconnect delays which has been achieved successfully by three-dimensional integrated circuit (3D IC). At this juncture, semiconductor industries utilize Cu-Cu bonding as a key technique for 3D IC integration. This review paper focuses on the key role of low temperature Cu-Cu bonding, renaissance of the low temperature bonding, and current research trends to achieve low temperature Cu-Cu bonding for 3D IC and heterogeneous integration applications.
TOPICS: Bonding, Low temperature, Architecture, Delays, Integrated circuits, Transistors, Semiconductors (Materials), Semiconductor industry
research-article  
Lei Shi, Lin Chen, David Wei Zhang, Evan Liu, Qiang Liu and Ching-I Chen
J. Electron. Packag   doi: 10.1115/1.4038245
Due to low cost and good electrical performance, wafer level chip scale packaging (WLCSP) has gained more attentions in both industry and academia. However, because the coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB), WLCSP technology still faces reliability challenges, such as the solder joint fragile life issue. In this paper, a new WLCSP design (WLCSP-PN) is proposed, based on the structure of WLCSP with Cu posts (WLCSP-P), to release the stress on the solder joints. In the new design, there is a space between the Cu post and the polymer which permits NiSn coating on the post sidewall. The overcoating enhances the solder-post interface where cracks were initiated and enlarges the IMC joint area to enhance the adhesion strength. Design of experiment (DOE) with the Taguchi method is adopted to obtain the sensitivity information of design parameters of the new design by the three-dimensional finite element model (FEM), leading to the optimized configuration. The finite element analysis results demonstrate that compared to WLCSP-P the proposed WLCSP-PN reduces the package displacement, equivalent stress and plastic strain energy density, and thus improves the fatigue life of solder joints.
TOPICS: Reliability, Semiconductor wafers, Thermomechanics, Packaging, Design, Solder joints, Finite element model, Stress, Fracture (Materials), Density, Thermal expansion, Adhesion, Coating processes, Coatings, Solders, Silicon, Taguchi methods, Finite element analysis, Polymers, Displacement, Fatigue life, Printed circuit boards

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