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Accepted Manuscripts

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research-article  
Takeru Kato, Ken Suzuki and Hideo Miura
J. Electron. Packag   doi: 10.1115/1.4036442
The dominant factors of electromigration (EM) resistance of electroplated copper thin film interconnections was investigated from the viewpoint of temperature and diffusion paths in the polycrystalline materials. EM test was performed to the interconnection in order to observe the degradation such as accumulation of copper and voids. Many voids and fracture of the interconnection occurred at the not cathode side but center of the interconnection due to large Joule heating under high current density. In addition, accumulation of copper and voids didn't appear homogeneously along all the grain boundaries. The crystallinity of grain boundaries in the interconnection was evaluated by image quality (IQ) value obtained from electron back-scatter diffraction analysis. The damaged grain boundaries mainly corresponded to grain boundaries with low crystallinity. Therefore, high Joule heating density and high speed diffusion of copper atoms along low crystallinity grain boundaries accelerated EM degradation of interconnections. The change of Joule heating density and activation energy of diffusion paths were evaluated by using annealed interconnections. Annealing of the interconnection improved the crystallinity and this improvement decreased the temperature of interconnection under high current density and increased the activation energy of grain boundary diffusion. These Change results in drastic difference of estimated lifetime of the interconnections. Thus, the lifetime of the interconnections under the EM loading is a strong function of their crystallinity of the interconnections. Therefore it is necessary to evaluate and control the crystallinity of the interconnections quantitatively using IQ value to assure their long-term reliability.
TOPICS: Thin films, Copper, Electrodiffusion, Grain boundaries, Heating, Joules, Diffusion (Physics), Temperature, Density, Current density, Electron backscatter diffraction, Grain boundary diffusion, Fracture (Materials), Fracture (Process), Atoms, Reliability, Annealing
research-article  
Valeriy Sukharev, Jun-Ho Choy, Armen Kteyan, Henrik Hovsepyan, Mark Nakamoto, Wei Zhao, Riko Radojcic, Uwe Muehle and Ehrenfried Zschech
J. Electron. Packag   doi: 10.1115/1.4036402
Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced 3D IC technologies are outlined. The growing need for a simulation-based design verification flow capable of analyzing and detecting across-die out-of-spec stress-induced variations in MOSFET/FinFET electrical characteristics is highlighted. A physics-based compact modeling methodology for multi-scale simulation of all contributing components of stress induced variability is described. A simulation flow that provides an interface between layout formats (GDS II, OASIS), and FEA-based package-scale tools, is also developed. This tool can be used to optimize the floorplan for different circuits and packaging technologies, and/or for the final design signoff, for all stress induced phenomena. Finally, a calibration technique based on fitting to measured electrical characterization data is presented, along with correlation of the electrical characteristics to direct physical strain measurements.
TOPICS: Physics, Flow (Dynamics), Plasma spectroscopy, Simulation, Stress, Electron mobility, Design, Finite element analysis, Modeling, Calibration, Circuits, Fittings, MOSFET transistors, Silicon, Strain measurement, Packaging
research-article  
Umut Zeynep Uras, Mehmet Arik and Enes Tamdogan
J. Electron. Packag   doi: 10.1115/1.4036403
In recent years, light emitting diodes (LEDs) have become an attractive technology for general and automotive illumination systems replacing old-fashioned incandescent and halogen systems. LEDs are preferable for automobile lighting applications due to its numerous advantages such as low power consumption, and precise optical control. Although these solid state lighting (SSL) products offer unique advantages, thermal management is one of the main issues due to severe ambient conditions and compact volume. Conventionally, tightly packaged double sided FR4 based printed circuit boards (PCBs) are utilized for both driver electronics components and LEDs. In fact, this approach will be a leading trend for advanced Internet of Things (IOT) applications embedded LED systems in the near future. Therefore, automotive lighting systems are already facing with tight-packaging issues. To evaluate thermal issues, a hybrid study of experimental and computational models are developed to determine the local temperature distribution on both sides of a 3-purpose automotive light engine for three different PCB approaches having different materials but the same geometry. Both results showed that FR4 PCB has a temperature gradient (TMaxBoard to TAmbient) of over 63°C. Moreover, a number of local hotspots occurred over FR4 PCB due to low thermal conductivity. Later, a metal core PCB is investigated to abate local hot spots. A further study has been performed with an advanced heat spreader board based on vapor chamber technology. Results showed that a thermal enhancement of 7.4% and 25.8% over Al metal core and FR4 based boards with the advanced vapor chamber substrate is observed. In addition to superior thermal performance, a significant amount of lumen extraction in excess of 15% is measured, and a higher reliability rate is expected.
TOPICS: Engines, Light-emitting diodes, Vapors, Metals, Electronics, Flat heat pipes, Printed circuit boards, Packaging, Temperature gradient, Reliability, Lumber, Thermal conductivity, Automobiles, Energy consumption, Geometry, Internet, Temperature distribution, Thermal management
research-article  
Leila Choobineh, Jared Jones and Ankur Jain
J. Electron. Packag   doi: 10.1115/1.4036404
3D integrated circuits (ICs) attract much interest due to several advantages over traditional microelectronics design, such as electrical performance improvement, reducing interconnect delay, and reducing manufacturing cost. While the power density of 3D ICs increases because of vertical integration, the available substrate area for heat removal does not change. Thermal modeling in 3D ICs is important for improving thermal and electrical performance. A number of numerical and analytical models have been developed for thermal analysis of 3D ICs and several experimental investigations on the thermal measurement of 3D ICs have been done. However, there is a relative lack of experimental work to determine key physical parameters in 3D ICs thermal design. One such important parameter in thermal analysis is the inter-die thermal resistance between adjacent die bonded together. This paper describes a novel experimental method to measure the value of inter-die thermal resistance between two die in a 3D IC. The effect of heating one die on the temperature of the other die in a two-die stack is measured over a short time period using high-speed data acquisition to negate the effect of boundary conditions. Numerical simulation is performed and based on a comparison between experimental data and the numerical model, the inter-die thermal resistance between the two die is determined. There is good agreement between experimental measurements and theoretically estimated value of the inter-die thermal resistance. Results from this paper are expected to assist in thermal design and management of 3D ICs.
TOPICS: Thermal resistance, Design, Computer simulation, Thermal analysis, Three-dimensional modeling, Heating, Microelectronic devices, Data acquisition, Power density, Manufacturing, Heat, Temperature, Boundary-value problems, Delays, Integrated circuits
research-article  
Wesam Adrugi, Yuri Muzychka and Kevin Pope
J. Electron. Packag   doi: 10.1115/1.4036405
In this paper, heat transfer enhancement using liquid-liquid Taylor flow in mini scale curved tubing for isothermal boundary conditions is examined. The copper tubing has an inner tube diameter of Di = 1.65 mm with different radii of curvature and lengths. Taylor flow is created using water and low viscosity silicone oils (0.65 cSt, 1 cSt, 3 cSt) to examine the effect of Prandtl number on heat transfer rates in curved tubing. A series of experiments are conducted using tubing with constant length and variable curvature, as well as variable length and constant curvature. The experimental results are compared with models for liquid-liquid Taylor flow in straight tubing and single-phase flow in curved tubes. The results of the research develop a new model for liquid-liquid Taylor flow in curved tubing. This research provides new insights into the effect of curvature on heat transfer enhancement for liquid-liquid Taylor flow in mini scale curved tubing, at a constant wall temperature.
TOPICS: Flow (Dynamics), Heat transfer, Tubing, Wall temperature, Water, Boundary-value problems, Oils, Petroleum, Prandtl number, Silicones, Copper, Viscosity
research-article  
Steven A. Isaacs, Diego A. Arias, Derek Hengeveld and Peter Hamlington
J. Electron. Packag   doi: 10.1115/1.4036406
Due to the compact and modular nature of CubeSats, thermal management has become a major bottleneck in system design and performance. In this study, we outline the development, initial testing, and modeling of a flat, conformable, lightweight, and efficient two-phase heat strap called FlexCool, currently being developed at Roccor. Using acetone as the working fluid, the heat strap has an average effective thermal conductivity of 2,149 W/m-K, which is approximately four times greater than the thermal conductivity of pure copper. Moreover, the heat strap has a total thickness of only 0.86 mm and is able to withstand internal vapor pressures as high as 930 kPa, demonstrating the suitability of the heat strap for orbital environments where pressure differences can be large. A reduced-order, closed-form theoretical model has been developed in order to predict the maximum heat load achieved by the heat strap for different design and operating parameters. The model is validated using experimental measurements and is used here in combination with a genetic algorithm to optimize the design of the heat strap with respect to maximizing heat transport capability.
TOPICS: Pressure, Vapor pressure, Heat, Fluids, Copper, Stress, Thermal conductivity, Design, Modeling, Optimization, Testing, Genetic algorithms, Thermal management, Flat heat pipes
research-article  
Steven Klein, Aleksandar Aleksov, Vijay Subramanian, Pramod Malatkar and Ravi Mahajan
J. Electron. Packag   doi: 10.1115/1.4036389
Stretchable electronics have been a subject of increased research over the past decade [1-3]. Although stretchable electronic devices are a relatively new area for the semiconductor/electronics industries, recent market research indicates the market could be worth more than 900 million dollars by 2023 [4]. At CES (Consumer Electronics Show) in January 2016, two commercial patches were announced which attach to the skin to measure information about the user’s vitals and environmental conditions [5]. This paper investigates mechanical testing methods designed to test the stretching capabilities of potential products across the electronics industry to help quantify and understand the mechanical integrity, response, and the reliability of these devices. Typically, the devices consist of stiff modules connected by stretchable traces [6]. There has been a test method proposed recently for harsh / high-rate testing (shock) of stretchable electronics [7]. The focus of the approach presented in the paper aims to simulate expected user conditions in the consumer and medical fields, whereas earlier research was focused on shock testing. In this paper, methods for simulating bi-axial and out-of-plane strains similar to what may occur in a wearable device on the human body are proposed. Electrical and / or optical monitoring (among other methods) can be used to determine cycles to failure depending on expected failure modes. Failure modes can include trace damage in stretchable regions, trace damage in functional component regions, or bulk stretchable material damage, among others.
TOPICS: Mechanical testing, Electronics, Damage, Shock (Mechanics), Failure mechanisms, Testing, Cycles, Failure, Skin, Semiconductors (Materials), Reliability, Biomedicine
research-article  
Vana Snigdha Tummala, Ahsan Mian, Nowrin H. Chamok, Dhruva Poduval, Mohammod Ali, Jallisa Clifford and Prasun Majumdar
J. Electron. Packag   doi: 10.1115/1.4036384
Engineered porous structures are being used in many applications including aerospace, electronics, biomedical and others. The objective of this paper is to study the effect of 3D printed porous microstructure on the dielectric characteristics for RF antenna applications. In this study, a sandwich construction made of a porous acrylonitrile butadiene styrene (ABS) thermoplastic core between two solid face sheets has been investigated. The porosity of the core structure has been varied by changing the fill densities or percent solid volume fractions in the 3D printer. Three separate sets of samples with dimensions of 50 mm x 50 mm x 5 mm are created at three different machine preset fill-densities each using LulzBot and Stratasys Dimension 3D printers. The printed samples are examined using a 3D X-ray microscope to understand pore distribution within the core region and uniformity of solid volumes. The nondestructively acquired 3D microscopy images are then post-processed to measure actual solid volume fractions within the samples. This measurement is important specifically for Dimension printed samples as the printer cannot be set for any specific fill density. The experimentally measured solid volume fractions are found to be different from the factory preset values for samples prepared using LulzBot printer. It is also observed that the resonant frequency for samples created using both the printers decreases with an increase in solid volume fraction, which is intuitively correct. The results clearly demonstrate the ability to control the dielectric properties of 3D printed structures based on prescribed fill density.
TOPICS: Density, Resonance, X-rays, Machinery, Dimensions, Sandwich construction, Aerospace industry, Microscopy, Porosity, Electronics, Microscopes, Biomedicine
research-article  
Krishna Tunga, Thomas A. Wassick and Maryse Cournoyer
J. Electron. Packag   doi: 10.1115/1.4036368
Fine pitch interconnects when used with 2D/2.5D packaging technology offers enormous potential towards decreasing signal latency and by making it possible to package increased electrical functionality within a given area. However, fine pitch interconnects present their own set of challenges not seen in packages with coarse pitch interconnects. Increased level of stresses within the Far Back End of Line (FBEOL) layers of the chip is the primary concern. Seven different types of 2D and 2.5D test vehicles with fine pitch and coarse pitch interconnects were built and tested for mechanical integrity by subjecting them to accelerated thermal cycling between -55ºC and 125ºC. Finite-element based mechanical modeling was done to determine the stress level within the FBEOL layers of these test vehicles. For all the tested assemblies, experimental data and modeling results showed a strong correlation between reduced pitch and increased level of stresses and increased incidence of failures within the FBEOL region. These failures were observed exclusively at the passivation layer and aluminum pad interface. Experimental data in conjunction with mechanical modeling was used to determine a safe level of stress at the aluminum to passivation layer interface. Global and local design changes were explored to determine their effect on the stresses at this interface. Several guidelines have been provided to reduce these stresses for a 2D/2.5D package assembly with fine pitch interconnects. Finally, a reliable low stress configuration, that takes into account all the design changes, has been proposed that is expected to be robust with very low risk of failure within the FBEOL region.
TOPICS: Aluminum, Stress, Failure, Modeling, Vehicles, Design, Finite element analysis, Manufacturing, Signals, Packaging, Risk
Review Article  
Yuyan Gao and Huanyu Cheng
J. Electron. Packag   doi: 10.1115/1.4036238
Specific function or application in electronics often requires assembly of heterogeneous materials in a single system. Schemes to achieve such goals are of critical importance for applications ranging from the study in basic cell biology to multifunctional electronics for diagnostics/therapeutics. In this review article, we will first briefly introduce a few assembly techniques such as micro-robotic assembly, guided self-assembly, additive manufacturing, and transfer printing. Among various heterogeneous assembly techniques, transfer printing represents a simple yet versatile tool to integrate vastly different materials or structures in a single system. By utilizing such technique, traditionally challenging tasks have been enabled and they include novel experimental platforms for study of 2D materials and cells, bio-integrated electronics such as stretchable and biodegradable devices, and 3D assembly with advanced materials such as semiconductors.
TOPICS: Manufacturing, Biomimetics, Electronics, Biology, Printing, Self-assembly, Advanced materials, Robotics, Semiconductors (Materials), Additive manufacturing, Biodegradation
Review Article  
Kaysar Rahim and Ahsan Mian
J. Electron. Packag   doi: 10.1115/1.4036239
The packaging of electronic and MEMS (micro-electromechanical systems) devices is an important part of the overall manufacturing process as it ensures mechanical robustness as well as required electrical/electromechanical functionalities. The packaging integration process involves the selection of packaging materials and technology, process design, fabrication, and testing. As the demand of functionalities of an electronic or MEMS device is increasing every passing year, chip size is getting larger and is occupying the majority of space within a package. This requires innovative packaging technologies so that integration can be done with less thermal/mechanical effect on the nearby components. Laser processing technologies for electronic and MEMS packaging have potential to obviate some of the difficulties associated with traditional packaging technologies and can become an attractive alternative for small-scale integration of components. As laser processing involves very fast localized and heating and cooling, the laser can be focused at micrometer scale to perform various packaging processes such as dicing, joining, patterning, etc. at the microscale with minimal or no thermal effect on surrounding material or structure. As such, various laser processing technologies are currently being explored by various researchers and also being utilized by electronic and MEMS packaging industries. This paper reviews the current and future trend of electronic and MEMS packaging and their manufacturing processes. Emphasis is given to the laser processing techniques that have the potential to revolutionize the future manufacturing of electronic and MEMS packages.
TOPICS: Lasers, MEMS packaging, Packaging, Manufacturing, Microelectromechanical systems, Microscale devices, Testing, Process design, Robustness, Temperature effects, Joining, Mechanical properties, Heating and cooling, MEMS packages
research-article  
Jingshi Meng and Abhijit Dasgupta
J. Electron. Packag   doi: 10.1115/1.4036187
Portable electronic devices are commonly exposed to shock and impact loading due to accidental drops. After external impact, internal collisions (termed “secondary impacts” in this study) between vibrating adjacent subassemblies of a product may occur if design guidelines fail to prevent such events. Secondary impacts can result in short acceleration pulses with much higher amplitudes and higher frequencies than those in conventional board level drop tests. Thus such pulses are likely to excite the high frequency resonances of printed wiring boards (PWBs) (including through-thickness ‘breathing’ modes) and also of miniature structures in assembled surface mount technology (SMT) components. Such resonant effects have a strong potential to damage the component, and therefore should be avoided. When the resonant frequency of a miniature structure (e.g. elements of a SMT MEMS component) in an SMT assembly is close to a natural frequency of the PWB, an amplified response is expected in the miniature structure. Components which are regarded as reliable under conventional qualification test methods, may still pose a failure risk when secondary impact is considered. This paper is the second part of a two-part series exploring the effect of secondary impacts in a printed wiring assembly (PWA). The first paper is this series focused on the ‘breathing’ mode of vibration generated in a PWB under secondary impact and this paper focuses on analyzing the effect of such ‘breathing’ modes on typical failure modes with different resonant frequencies in SMT applications. The results demonstrate distinctly different sensitivity of each failure mode to the impacts.
TOPICS: Failure mechanisms, Electrical wires, Surface mount components, Resonance, Printed circuit boards, Manufacturing, Collisions (Physics), Shock (Mechanics), Microelectromechanical systems, Design, Surface mount technology, Vibration, Failure, Risk, Damage
research-article  
Thong Kok Law, Fannon Lim, Yun Li, XuePeng Puan, G.K.E. Sng and Jin Wah Ronnie Teo
J. Electron. Packag   doi: 10.1115/1.4036066
The phosphor and die bonding configuration affect the optical efficiency and thermal performance in phosphor-coated white LEDs. In this paper, light emission studies reveal that the chromaticity shift and light extraction losses depend on the uniformity of phosphor particles deposited over the LED surface. A non-uniform and sparse phosphor layer affects the correlated color temperature (CCT) and the spectral Y-B ratio due to the disproportionate contribution of light emission between the LED device and the phosphor layer. Furthermore, the Y-B ratio was observed to reduce with temperature due to higher Stoke's energy and light extraction losses in the phosphor layer. As a result, the Y-B ratio exhibits an inverse relationship with the package's thermal resistance as a function of temperature. On the other hand, the thermal performance of a LED package is dependent on the die-bonding configurations (conventional and flip-chip). Due to the improved heat dissipation capabilities in flip-chip bonding, the temperature rise and thermal resistance of the package was observed to reduce with temperature. By alleviating the heat accumulation in the package, more stable colorimetric properties such as CCT and Y-B ratio can be achieved.
TOPICS: Light-emitting diodes, Packaging, Phosphors, Temperature, Bonding, Thermal resistance, Heat, Light emission, Flip-chip, Particulate matter, Energy dissipation
research-article  
Joel Thambi, Andreas Schiessl, Manuela Waltz, Klaus-Dieter Lang and Ulrich Tetzlaff
J. Electron. Packag   doi: 10.1115/1.4035850
This paper, explicitly establishes a modified creep model of a Sn3.8Ag0.7Cu alloy using a physical based micro-mechanical modelling technique. Through experimentation and reformulation steady-state creep behavior, is analyzed with minimum strain rates for different temperatures 35°C, 80°C, and 125°C. The new modified physical creep model is proposed, by understanding the respective precipitate strengthened deformation mechanism, seeing the dependency of the activation energy over the temperature along with stress and fi-nally by integrating the subgrain size dependency λss. The new model is found to accurately modelling the creep behavior of Lead free solder alloy by combining the physical state variables. The features of the creep model can be explored further by changing the physical variable such as subgrain size to establish a struc-ture - property relationship for a better solder joint reliability performance.
TOPICS: Creep, Alloys, Modeling, Lead-free solders, Temperature, Reliability, Stress, Solder joints, Steady state, Deformation

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