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Accepted Manuscripts

BASIC VIEW  |  EXPANDED VIEW
Guest Editorial  
Kaushik Mysore, Sreekant Narumanchi, Ercan Dede and Reza Khiabani
J. Electron. Packag   doi: 10.1115/1.4039090
Guest Editorial for JEP Special Section on InterPACK 2017
research-article  
Nicolas Lamaison, Raffaele Luca Amalfi, Todd Salamon, Jackson B. Marcinichen and John R. Thome
J. Electron. Packag   doi: 10.1115/1.4039091
Gravity-driven two-phase liquid cooling systems using flow boiling within micro-scale evaporators are becoming a game-changing solution for electronics cooling. The optimization of the system's filling ratio can however become a challenging problem for a system operating over a wide range of cooling capacities and temperature ranges. The benefits of a liquid accumulator to overcome this difficulty are evaluated in the present paper. An experimental thermosyphon cooling system was built to cool multiple electronic components up to a power dissipation of 1800 W. A double-ended cylinder with a volume of 150 cm3 is evaluated as the liquid accumulator for two different system volumes (associated to two different condensers). Results demonstrated that the liquid accumulator provided robust thermal performance as a function of filling ratio for the entire range of heat loads tested. In addition, the present liquid accumulator was more effective for a small volume system, 599 cm3, than for a large volume system, 1169 cm3, in which the relative size of the liquid accumulator increased from 12.8 % to 25% of the total system's volume.
TOPICS: Cooling systems, Experimental analysis, Secondary cells, Electronics, Computer cooling, Gravity (Force), Flow (Dynamics), Heat, Temperature, Cooling, Stress, Energy dissipation, Boiling, Electronic components, Microscale devices, Optimization, Condensers (steam plant), Cylinders
research-article  
Jayati Athavale, Yogendra Joshi and Minami Yoda
J. Electron. Packag   doi: 10.1115/1.4039025
This paper presents an experimentally validated room-level computational fluid dynamics (CFD) model for raised-floor data center configurations employing active tiles. Active tiles are perforated floor tiles with integrated fans, which increase the local volume flow rate by redistributing the cold air supplied by the computer room air conditioning (CRAC) unit to the under-floor plenum. The numerical model of the data center room consists of one cold aisle with 12 racks arranged on both sides and three CRAC units sited around the periphery of the room. The commercial CFD software package Future Facilities 6SigmaDCX is used to develop the model for three configurations: (a) an aisle populated with 10 (i.e., all) passive tiles (b) a single active tile and 9 passive tiles in the cold aisle (c) an aisle populated with all active tiles. The predictions from the CFD model are found to be in good agreement with the experimental data, with an average discrepancy between the measured and computed values for total flow rate and rack inlet temperature less than 4% and 1.7 ?, respectively. The validated models were then used to simulate steady state and transient scenarios following cooling failure. This physics-based and experimentally validated room-level model can be used for temperature and flow distributions prediction and identifying optimal number and locations of active tiles for hot spot mitigation in data centers.
TOPICS: Computational fluid dynamics, Data centers, Tiles, Flow (Dynamics), Temperature, Cooling, Air conditioning, Computer simulation, Transients (Dynamics), Fans, Computers, Computer software, Physics, Failure, Steady state
research-article  
Ercan M. Dede, Feng Zhou, Paul Schmalenberg and Tsuyoshi Nomura
J. Electron. Packag   doi: 10.1115/1.4039020
Rapid advancement of modern electronics has pushed the limits of traditional thermal management techniques. Novel approaches to the manipulation of the flow of heat in electronic systems have potential to open new design spaces. Here, the field of thermal metamaterials as it applies to electronics is briefly reviewed. Recent research and development of thermal metamaterial systems with anisotropic thermal conductivity for the manipulation of heat flow in ultra-thin composites is explained. An explanation of fundamental experimental studies on heat flow control using standard printed circuit board technology follows. From this, basic building blocks for heat flux cloaking, focusing, and reversal are reviewed, and their extension to a variety of electronics applications is emphasized. While device temperature control, thermal energy harvesting, and electro-thermal circuit design are the primary focus, some discussion on the extension of thermal-guiding structures to device-scale applications is provided. In total, a holistic view is offered of the myriad of possible applications of thermal metamaterials to heat flow control in future electronics.
TOPICS: Heat, Flow control, Metamaterials, Electronics, Flow (Dynamics), Heat flux, Printed circuit boards, Thermal management, Composite materials, Temperature control, Thermal energy, Industrial research, Blocks (Building materials), Circuit design, Anisotropy, Space, Thermal conductivity, Design, Electronic systems
research-article  
Gonzalez Cuadrado David, Marconnet Amy and Paniagua Guillermo
J. Electron. Packag   doi: 10.1115/1.4039026
Large thermal gradients represent major operational hazards in microprocessors, hence there is a critical need to monitor possible hot spots both accurately and in real-time. Thermal monitoring in a microprocessor is typically performed using temperature sensors embedded in the electronic board. The location of the temperature sensors is primarily determined by the sensor space claim rather than the ideal location for thermal management. This manuscript presents an optimization methodology to determine the most beneficial locations for the temperature sensors inside of the microprocessors, based on input from high resolution surface infrared thermography combined with inverse heat transfer solvers to predict hot spot locations. The infrared image is used to obtain the temperature over the processor surface, and subsequently delivers the input to a 3D inverse heat conduction methodology, used to determine the temperature field within the processor. In this paper, simulated thermal maps are utilized to assess the accuracy of this method. The inverse methodology is based on a function specification method combined with a sequential regularization in order to increase accuracy in the results. Together with the number of sensors, the temperature field within the processor is then used to determine the optimal location of the temperature sensors using a genetic algorithm optimization combined with a Kriging interpolation. This combination of methodologies was validated against the Finite Element Analysis of a chip incorporating heaters and temperature sensors. An uncertainty analysis of the inverse methodology and the Kriging interpolation was performed separately to assess the reliability of the procedure.
TOPICS: Heat conduction, Heat transfer, Integrated circuits, Interpolation, Temperature sensors, Temperature, Sensors, Optimization, Genetic algorithms, Thermography, Reliability, Resolution (Optics), Finite element analysis, Thermal management, Temperature gradient, Hazards, Uncertainty analysis
research-article  
Sandeep Mallampati, Liang Yin, David Shaddock, Harry Schoeller and Junghyun Cho
J. Electron. Packag   doi: 10.1115/1.4039027
Predominant high melting point solders for high temperature and harsh environment electronics are Pb-based systems, which are being subjected to RoHS regulations because of their toxic nature. In this study, high bismuth (Bi) alloy compositions with Bi-XSb-10Cu (X from 10 wt.% to 20 wt.%) were designed and developed to evaluate their potential as high-temperature, Pb-free replacements. The die-attach joints made out of Bi-15Sb-10Cu alloy exhibited an average shear strength of 24 MPa, which is comparable to that of commercially available high Pb solders. In addition, heat dissipation capabilities, using flash diffusivity, were measured on the die-attach assembly, compared to the corresponding bulk alloys. The thermal conductivity of all the Bi-Sb alloys was higher than that of pure Bi. By creating high volume fraction of precipitates in a die-attach joint microstructure, it was feasible to further increase thermal conductivity of this joint to 24 W/m·K, which is three times higher than that of pure Bi (8 W/m·K). Bi-15Sb-10Cu alloy has shown limited plastic deformation in room temperature tensile testing, in which premature fracture occurred via the cracks propagated on the (111) cleavage planes of rhombohedral crystal structure of the Bi(Sb) matrix. The same alloy has, however, shown up to 7% plastic strain under tension when tested at 175°C. The cleavage planes, which became oriented at smaller angles to the tensile stress, contributed to improved plasticity in the high temperature test.
TOPICS: Electronics, High temperature, Alloys, Solders, Tension, Fracture (Materials), Thermal conductivity, Melting point, Regulations, Shear strength, Tensile testing, Manufacturing, Energy dissipation, Plasticity, Deformation, Heat, Temperature, Crystal structure
research-article  
Sadegh Khalili, Mohammad Tradat, Kourosh Nemati, Mark Seymour and Bahgat Sammakia
J. Electron. Packag   doi: 10.1115/1.4039028
In raised floor data centers, tiles with high open area ratio or complex understructure are used to fulfill the demand of today's high-density computing. Using more open tiles reduces the pressure drop across the raised floor with the potential advantages of increased airflow and lower noise. However, it introduces the disadvantage of increased non-uniformity of airflow distribution. In addition, there are various tile designs available on the market with different opening shapes or understructures. Furthermore, a physical separation of cold and hot aisles (containment) has been introduced to minimize the mixing of cold and hot air. In this study, three types of floor tiles with different open area, opening geometry, and understructure are considered. Experimentally validated detail models of tiles were implemented in CFD simulations to address the impact of tile design on the cooling of IT equipment in both open and enclosed aisle configurations. Also, impacts of under-cabinet leakage on the IT equipment inlet temperature in the provisioned and under-provisioned scenarios are studied. In addition, a predictive equation for the critical under-provisioning point that can lead to a no-flow condition in IT equipment with weaker airflow systems is presented. Finally, the impact of tile design on thermal performance in a partially enclosed aisle with entrance doors is studied and discussed.
TOPICS: Design, Tiles, Air flow, Simulation, Noise (Sound), Computational fluid dynamics, Density, Flow (Dynamics), Temperature, Cooling, Separation (Technology), Doors, Leakage, Containment, Engineering simulation, Data centers, Geometry, Pressure drop, Shapes
research-article  
Yu Tang, Shaoming Luo, Guoyuan Li, Zhou Yang and Chaojun Hou
J. Electron. Packag   doi: 10.1115/1.4038861
The ripening growth kinetics of interfacial Cu6Sn5 grains between Cu substrates and Sn-3.0Ag-0.5Cu-xTiO2 (x = 0, 0.02, 0.05, 0.1, 0.3, and 0.6 wt.%) (SAC305-xTiO2) solders were investigated. The results show that the Cu6Sn5 grain morphology is affected by the solder composition and the reflow time. The Cu6Sn5 grain size decreases upon addition of TiO2 and shows a significant decrease when the TiO2 nanoparticle fraction is increased to 0.1 wt.%. At higher TiO2 nanoparticle fractions, the Cu6Sn5 grain size increases slightly. The growth of the Cu6Sn5 grains is mainly supplied by the flux of the interfacial reaction and the flux of ripening; the ripening flux plays a dominant role because it is approximately one order of magnitude greater than the interfacial reaction flux. The ripening growth of the Cu6Sn5 grains in the TiO2-containing solder joints is reduced more effectively than that of the Cu6Sn5 grains in the TiO2-free joint. For the SAC305/Cu and SAC305-0.6TiO2/Cu solder joints, the particle size distribution (PSD) of the Cu6Sn5 grains is well fit with the Marqusee and Ross (MR) model when the r/ is less than 1, and it is consistent with the flux-driven ripening (FDR) model when the r/ is greater than 1. For the SAC305-0.1TiO2/Cu solder joint, the Cu6Sn5 grains with a nearly hemispheric scallop shape and the PSD of the Cu6Sn5 grains show good agreement with the FDR model.
TOPICS: Tin, Solder joints, Solders, Nanoparticles, Grain size, Particle size, Shapes
Errata  
Richard C. Jaeger, Mohammad Motalab, Safina Hussain and Jeffrey C. Suhling
J. Electron. Packag   doi: 10.1115/1.4038735
The conjecture discussed in the referenced paper was backed up by measurements and simulation results, but not mathematically proven. A proof based on impedance parameter reciprocity is presented, and a sign error is corrected.
TOPICS: Electrons, Bridges (Structures), Sensors, Wire, Stress, Errors, Silicon, Simulation results
research-article  
X.J. Yao, J.J. Fang and W.J. (Chris) Zhang
J. Electron. Packag   doi: 10.1115/1.4038391
The notion of permeability is very important in understanding and modeling the flow behavior of fluids in a special type of porous medium (i.e., the underfill flow in flip-chip packaging). This paper presents a new concept regarding permeability in a porous medium, namely two types of permeability: superficial permeability (with consideration of both the pore cross-section area and the solid matrix cross-section area) and pore permeability (with consideration of the pore across-section area only). Subsequently, the paper proposes an analytical model (i.e., equation) for the pore permeability and superficial permeability of an underfill porous medium in a flip-chip packaging, respectively. The proposed model along with several similar models in literature is compared with a reliable numerical model developed with the CFD (computational fluid dynamics) technique, and the result of the comparison shows that the proposed model for permeability is the most accurate one among all the analytical models in literature. The main contributions of the paper are: (1) the provision of a more accurate analytical model for the permeability of an underfill porous medium in flip-chip packaging, (2) the finding of two types of permeability depending on how the cross-section area is taken, and (3) the correction of an error in the other's model in literature.
TOPICS: Permeability, Packaging, Flip-chip, Porous materials, Flow (Dynamics), Computational fluid dynamics, Modeling, Errors, Fluids, Computer simulation
Review Article  
Asisa Kumar Panigrahy and Kuan-Neng Chen
J. Electron. Packag   doi: 10.1115/1.4038392
Arguably, the IC industry has received robust scientific and technological attention due to the ultra-small and extremely fast transistors since past four decades that consents to Moore's law. The introduction of new interconnect materials as well as innovative architectures has aided for large scale miniaturization of devices, but their contributions were limited. Thus, the focus has shifted towards the development of new integration approaches that reduce the interconnect delays which has been achieved successfully by three-dimensional integrated circuit (3D IC). At this juncture, semiconductor industries utilize Cu-Cu bonding as a key technique for 3D IC integration. This review paper focuses on the key role of low temperature Cu-Cu bonding, renaissance of the low temperature bonding, and current research trends to achieve low temperature Cu-Cu bonding for 3D IC and heterogeneous integration applications.
TOPICS: Bonding, Low temperature, Architecture, Delays, Integrated circuits, Transistors, Semiconductors (Materials), Semiconductor industry
research-article  
Lei Shi, Lin Chen, David Wei Zhang, Evan Liu, Qiang Liu and Ching-I Chen
J. Electron. Packag   doi: 10.1115/1.4038245
Due to low cost and good electrical performance, wafer level chip scale packaging (WLCSP) has gained more attentions in both industry and academia. However, because the coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB), WLCSP technology still faces reliability challenges, such as the solder joint fragile life issue. In this paper, a new WLCSP design (WLCSP-PN) is proposed, based on the structure of WLCSP with Cu posts (WLCSP-P), to release the stress on the solder joints. In the new design, there is a space between the Cu post and the polymer which permits NiSn coating on the post sidewall. The overcoating enhances the solder-post interface where cracks were initiated and enlarges the IMC joint area to enhance the adhesion strength. Design of experiment (DOE) with the Taguchi method is adopted to obtain the sensitivity information of design parameters of the new design by the three-dimensional finite element model (FEM), leading to the optimized configuration. The finite element analysis results demonstrate that compared to WLCSP-P the proposed WLCSP-PN reduces the package displacement, equivalent stress and plastic strain energy density, and thus improves the fatigue life of solder joints.
TOPICS: Reliability, Semiconductor wafers, Thermomechanics, Packaging, Design, Solder joints, Finite element model, Stress, Fracture (Materials), Density, Thermal expansion, Adhesion, Coating processes, Coatings, Solders, Silicon, Taguchi methods, Finite element analysis, Polymers, Displacement, Fatigue life, Printed circuit boards

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